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AD7707 Datasheet(PDF) 11 Page - Analog Devices

Part No. AD7707
Description  3-Channel 16-Bit, Sigma-Delta ADC
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7707 Datasheet(HTML) 11 Page - Analog Devices

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AD7707
Rev. B | Page 10 of 52
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SCLK 1
MCLK IN 2
MCLK OUT 3
CS 4
DGND
20
DVDD
19
DIN
18
DOUT
17
RESET 5
DRDY
16
AVDD 6
AGND
15
AIN1 7
REF IN(–)
14
LOCOM 8
REF IN(+)
13
AIN2 9
VBIAS
12
AIN3 10
HICOM
11
AD7707
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SCLK
Serial Clock, Schmitt-Triggered Logic Input. An external serial clock is applied to this input to access serial data
from the AD7707. This serial clock can be a continuous clock with all data transmitted in a continuous train of
pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to the AD7707 in
smaller batches of data.
2
MCLK IN
Master Clock Signal for the Device. This can be provided in the form of a crystal/resonator or external clock. A
crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be
driven with a CMOS-compatible clock and MCLK OUT left unconnected. The part can be operated with clock
frequencies in the range of 500 kHz to 5 MHz.
3
MCLK OUT
When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN
and MCLK OUT. If an external clock is applied to MCLK IN, MCLK OUT provides an inverted clock signal. This clock
can be used to provide a clock source for external circuitry and is capable of driving one CMOS load. If the user
does not require it, this MCLK OUT can be turned off via the CLKDIS bit of the clock register. This ensures that the
part is not wasting unnecessary power driving capacitive loads on MCLK OUT.
4
CS
Chip Select. This pin is an active low logic input used to select the AD7707. With this input hard-wired low, the
AD7707 can operate in its 3-wire interface mode with SCLK, DIN, and DOUT used to interface to the device. CS
can be used to select the device in systems with more than one device on the serial bus or as a frame
synchronization signal in communicating with the AD7707.
5
RESET
Logic Input. Active low input that resets the control logic, interface logic, calibration coefficients, digital filter, and
analog modulator of the part to power-on status.
6
AVDD
Analog Supply Voltage, 2.7 V to 5.25 V Operation.
7
AIN1
Low Level Analog Input Channel 1. This is used as a pseudo differential input with respect to LOCOM.
8
LOCOM
Common Input for Low Level Input Channels. Analog inputs on AIN1 and AIN2 must be referenced to this input.
9
AIN2
Low Level Analog Input Channel 2. This is used as a pseudo differential input with respect to LOCOM.
10
AIN3
Single-Ended High Level Analog Input Channel with respect to HICOM.
11
HICOM
Common Input for igh evel nput hannel. Analog input on AIN3 must be referenced to this input.
12
VBIAS
VBIAS is used to level shift the high level input channel signal. This signal is used to ensure that the AIN(+) and
AIN(−) signals seen by the internal modulator are within its common-mode range. VBIAS is normally connected
to 2.5 V when AVDD = 5 V and 1.225 V when AVDD = 3 V.
13
REF IN(+)
Reference Input. Positive input of the differential reference input to the AD7707. The reference input is
differential with the provision that REF IN(+) must be greater than REF IN(−). REF IN(+) can lie anywhere between
AVDD and AGND.
14
REF IN(−)
Reference Input. Negative input of the differential reference input to the AD7707. The REF IN(−) can lie anywhere
between AVDD and AGND provided that REF IN(+) is greater than REF IN(−).
15
AGND
Analog Ground. Ground reference point for the AD7707’s internal analog circuitry.
16
DRDY
Logic Output. A logic low on this output indicates that a new output word is available from the AD7707 data
register. The DRDY pin returns high upon completion of a read operation of a full output word. If no data read has
taken place between output updates, the DRDY line returns high for 500 × tCLK IN cycles prior to the next output
update. While DRDY is high, a read operation should neither be attempted nor in progress to avoid reading from
the data register as it is being updated. The DRDY line returns low again when the update has taken place. DRDY
is also used to indicate when the AD7707 has completed its on-chip calibration sequence.
17
DOUT
Serial Data Output with Serial Data Being Read from the Output Shift Register on the Part. This output shift
register can contain information from the setup register, communications register, clock register, or data register,
depending on the register selection bits of the communications register.


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