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AD7707 Datasheet(PDF) 29 Page - Analog Devices

Part No. AD7707
Description  3-Channel 16-Bit, Sigma-Delta ADC
Download  53 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7707 Datasheet(HTML) 29 Page - Analog Devices

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AD7707
Rev. B | Page 28 of 52
DIGITAL FILTERING
The AD7707 contains an on-chip low-pass digital filter that
processes the output of the part’s Σ-Δ modulator. Therefore, the
part not only provides the analog-to-digital conversion function
but also provides a level of filtering. There are a number of system
differences when the filtering function is provided in the digital
domain rather than the analog domain and the user should be
aware of these.
First, because digital filtering occurs after the ADC process, it
can remove noise injected during the conversion process. Analog
filtering cannot do this. Also, the digital filter can be made
programmable far more readily than an analog filter. Depending
on the digital filter design, this gives the user the capability of
programming cutoff frequency and output update rate.
On the other hand, analog filtering can remove noise superim-
posed on the analog signal before it reaches the ADC. Digital
filtering cannot do this and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator
and digital filter, even though the average value of the signal is
within limits. To alleviate this problem, the AD7707 has over-
range headroom built into the Σ-Δ modulator and digital filter,
which allows overrange excursions of 5% above the analog
input range. If noise signals are larger than this, consideration
should be given to analog input filtering, or to reducing the input
channel voltage so that its full scale is half that of the analog input
channel full scale. This provides an overrange capability greater
than 100% at the expense of reducing the dynamic range by one
bit (50%).
In addition, the digital filter does not provide any rejection at
integer multiples of the digital filter’s sample frequency. However,
the input sampling on the part provides attenuation at multiples
of the digital filter’s sampling frequency so that the unattenuated
bands actually occur around multiples of the sampling frequency, fS
(as defined in Table 27). Thus, the unattenuated bands occur at
n × fS (where n = 1, 2, 3…). At these frequencies, there are
frequency bands of ±f3 dB width (f3 dB is the cutoff frequency of
the digital filter) where noise passes unattenuated to the output.
FILTER CHARACTERISTICS
The AD7707’s digital filter is a low-pass filter with a (sinx/x)3
response (also called sinc3). The transfer function for this filter
is described in the z domain by:
3
1
1
1
1
)
(
×
=
Z
Z
N
z
H
N
and in the frequency domain by:
3
/
(
)
/
(
1
)
(
S
S
f
f
SIN
f
f
N
SIN
N
f
H
×
π
×
π
×
×
where N is the ratio of the modulator rate to the output rate.
Phase response:
Rad
f
f
N
H
S
/
)
2
(
3
×
π
=
Figure 16 shows the filter frequency response for a cutoff
frequency of 2.62 Hz, which corresponds to a first filter notch
frequency of 10 Hz. The plot is shown from dc to 65 Hz. This
response is repeated at either side of the digital filter’s sample
frequency and at either side of multiples of the filter’s sample
frequency.
The response of the filter is similar to that of an averaging filter,
but with a sharper roll-off. The output rate for the digital filter
corresponds with the positioning of the first notch of the filter’s
frequency response. Thus, for the plot of Figure 16 where the
output rate is 10 Hz, the first notch of the filter is at 10 Hz. The
notches of this (sinx/x)3 filter are repeated at multiples of the
first notch. The filter provides attenuation of better than 100 dB
at these notches.
FREQUENCY (Hz)
0
–140
–240
0
10
20
30
40
50
60
–20
–160
–180
–60
–100
–40
–80
–200
–220
–120
Figure 16. Frequency Response of AD7707 Filter
Simultaneous 50 Hz and 60 Hz rejection is obtained by placing
the first notch at 10 Hz. Operating with an update rate of 10 Hz
places notches at both 50 Hz and 60 Hz giving better than 100 dB
rejection at these frequencies.
The cutoff frequency of the digital filter is determined by the value
loaded to Bit FS0 to Bit FS2 in the clock register. Programming
a different cutoff frequency via FS0, FS1, and FS2 does not alter
the profile of the filter response; it changes the frequency of the
notches. The output update of the part and the frequency of the
first notch correspond.
Because the AD7707 contains this on-chip, low-pass filtering, a
settling time is associated with step function inputs and data on
the output will be invalid after a step change until the settling
time has elapsed. The settling time depends upon the output rate
chosen for the filter. The settling time of the filter to a full-scale
step input can be up to four times the output data period. For a
synchronized step input (using the FSYNC function), the settling
time is three times the output data period.


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