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STK12C68-C20 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers

Part No. STK12C68-C20
Description  8k x 8 AUTOSTORE NVSRAM QUANTUM TRAP CMOS NONVOLATILE STATIC RAM
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Maker  ETC [List of Unclassifed Manufacturers]
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STK12C68-C20 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers

 
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STK12C68
July 1999
4-43
SRAM READ CYCLES #1 & #2
(VCC = 5.0V ± 10%)
b, f
Note h:
W and HSB must be high during SRAM READ cycles.
Note i:
Device is continuously selected with E and G both low.
Note j:
Measured
± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledh, i
SRAM READ CYCLE #2: E Controlledh
NO.
SYMBOLS
PARAMETER
STK12C68-20
STK12C68-25
STK12C68-35
STK12C68-45
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1tELQV
tACS
Chip Enable Access Time
20
25
35
45
ns
2tAVAV
h
tRC
Read Cycle Time
20
25
35
45
ns
3tAVQV
i
tAA
Address Access Time
22
25
35
45
ns
4tGLQV
tOE
Output Enable to Data Valid
8
10
15
20
ns
5tAXQX
i
tOH
Output Hold after Address Change
5
5
5
5
ns
6tELQX
tLZ
Chip Enable to Output Active
5
5
5
5
ns
7tEHQZ
j
tHZ
Chip Disable to Output Inactive
7
10
13
15
ns
8tGLQX
tOLZ
Output Enable to Output Active
0
0
0
0
ns
9tGHQZ
j
tOHZ
Output Disable to Output Inactive
7
10
13
15
ns
10
tELICCH
g
tPA
Chip Enable to Power Active
0
0
0
0
ns
11
tEHICCL
g
tPS
Chip Disable to Power Standby
25
25
35
45
ns
DATA VALID
5
tAXQX
3
tAVQV
DQ (DATA OUT)
ADDRESS
2
tAVAV
6
tELQX
STANDBY
DATA VALID
8
tGLQX
4
tGLQV
DQ (DATA OUT)
E
ADDRESS
2
tAVAV
G
ICC
ACTIVE
1
tELQV
10
tELICCH
11
tEHICCL
7
tEHQZ
9
tGHQZ


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