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NCP1378PG Datasheet(PDF) 10 Page - ON Semiconductor |
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NCP1378PG Datasheet(HTML) 10 Page - ON Semiconductor |
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10 / 16 page  NCP1378 http://onsemi.com 10 The NCP1378 demagnetization detection pad features a specific component arrangement as detailed by Figure 21. In this picture, the zener diodes network protect the IC against any potential ESD discharge that could appear on the pins. The first ESD diode connected to the pad, exhibits a parasitic capacitance. When this parasitic capacitance (10 pF typically) is combined with Rdem, a restart delay is created and the possibility to switch right in the drain−source wave exists. This guarantees QR operation with all the associated benefits (low EMI, no turn−on losses etc.). Rdem should be calculated to limit the maximum current flowing through pin 1 to less than +3.0 mA/−2.0 mA: If during turn−on, the auxiliary winding delivers 30 V (at the highest line level), then the minimum Rdem value is defined by: 30 + 0.7/3.0 mA = 10.2 k W. This value will be further increased e.g. to introduce a restart delay and also a slight filtering in case of high leakage energy. Figure 22 portrays a typical VDS shot at nominal output power. Figure 22. The NCP1378 Operates in Borderline/Critical Operation 400 300 200 100 0 Overvoltage Protection The overvoltage protection works by sampling the plateau voltage 4.5 ms after the turn−off sequence. This delay guarantees a clean plateau, providing that the leakage inductance ringing has been fully damped. If this would not be the case, the designer should install a small RC damper across the transformer primary inductance connections. Figure 23 shows where the sampling occurs on the auxiliary winding. Figure 23. A Voltage Sample is Taken 4.5 ms After the Turn−Off Sequence 8.0 6.0 4.0 2.0 0 SAMPLING HERE 4.5 ms When an OVP condition has been detected, the NCP1378 enters a latchoff phase and stops all switching operations. The controller stays fully latched in this position and the startup source being still active, it keeps the VCC going up and down between 8.4 V and 5.5 V. This state lasts until the VCC is cycled down to 4.0 V, e.g. when the user unplugs the power supply from the mains outlet. By default, the OVP comparator is biased to a 5.2 V reference level and pin1 is directly routed to the comparator. As a result, when Vpin1 reaches 5.2 V, the OVP comparator is triggered. The threshold can thus be adjusted by either modifying the power winding to auxiliary winding turn ratios to match this 5.2 V level or insert a resistor from pin1 to ground to cope with your design requirement. Latching Off the NCP1378 In certain cases, it can be very convenient to externally shut down permanently the NCP1378 via a dedicated signal, e.g. coming from a temperature sensor (Figure 24). The reset occurs when the user unplugs the power supply from the mains outlet. To trigger the latchoff by an external signal, a simple PNP transistor can do the work, as Figure 25 shows. |
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