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MCF5274LVM133 Datasheet(PDF) 6 Page - Motorola, Inc |
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MCF5274LVM133 Datasheet(HTML) 6 Page - Motorola, Inc |
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6 / 76 page  MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Preliminary Features Freescale Semiconductor 6 — One FIFO RAM per endpoint (2-Kbyte total) — Dedicated 1-Kbyte descriptor RAM, accessible from the Slave bus — Remote wake-up • Hardware cryptography accelerator (optional) — Random number generator — DES/3DES/AES block cipher engine — MD5/SHA-1/HMAC accelerator • Three Universal Asynchronous/synchronous Receiver Transmitters (UARTs) — Serial communication channel — 16-bit divider for clock generation — Internal channel control logic — Interrupt control logic — Maskable interrupts — DMA support — Programmable clock-rate generator — Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity — Up to 2 stop bits in 1/16 increments — Error-detection capabilities — Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines — Transmit and receive FIFO buffers •I2C Module — Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads — Fully compatible with industry-standard I2C bus — Master or slave modes support multiple masters — Automatic interrupt generation with programmable level • Queued Serial Peripheral Interface (QSPI) — Full-duplex, three-wire synchronous transfer — Up to four chip selects available — Master operation — Programmable master bit rates — Up to 16 preprogrammed transfers • Four 32-bit Timers with DMA request capability • Pulse width modulation (PWM) unit — Four identical channels • Software Watchdog Timer |
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Similar Description - MCF5274LVM133 |
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