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M29W400BB90ZA6 Datasheet(PDF) 3 Page - STMicroelectronics |
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M29W400BB90ZA6 Datasheet(HTML) 3 Page - STMicroelectronics |
3 / 25 page 3/25 M29W400BT, M29W400BB Figure 4. TFBGA Connections (Top view through package) AI03988 B A 4 3 2 1 G F H DQ15 A–1 A7 A3 DQ10 DQ8 E DQ13 DQ11 DQ9 G VSS DQ6 DQ1 VSS DQ14 A12 NC A17 A4 A14 A10 NC NC A6 A2 RP A8 DQ4 DQ3 VCC DQ12 A9 BYTE A15 A11 NC A1 A16 DQ7 DQ5 DQ2 A0 NC DQ0 A5 E D C RB W A13 6 5 The blocks in the memory are asymmetrically ar- ranged, see Tables 3 and 4, Block Addresses. The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the micro- processor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored. Chip Enable, Output Enable and Write Enable sig- nals control the bus operation of the memory. They allow simple connection to most micropro- cessors, often without additional logic. The memory is offered in TSOP48 (12 x 20mm), TFBGA48 (0.8mm pitch) and SO44 packages and it is supplied with all the bits erased (set to ’1’). |
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