Serial Interface

Initialization After Power-Up

and Starting a Conversion

Upon initial power-up, the MAX1224/MAX1225 require a

complete conversion cycle to initialize the internal cali-

bration. Following this initial conversion, the part is ready

for normal operation. This initialization is only required

after a hardware power-up sequence and is not required

after exiting partial or full power-down mode.

To start a conversion, pull CNVST low. At CNVST’s

falling edge, the T/H enters its hold mode and a conver-

sion is initiated. SCLK runs the conversion and the data

can then be shifted out serially on DOUT.

Timing and Control

Conversion-start and data-read operations are con-

trolled by the CNVST and SCLK digital inputs. Figures 1

and 5 show timing diagrams, which outline the serial-

interface operation.

A CNVST falling edge initiates a conversion sequence:

the T/H stage holds the input voltage, the ADC begins

to convert, and DOUT changes from high impedance to

logic low. SCLK is used to drive the conversion

process, and it shifts data out as each bit of the conver-

sion is determined.

SCLK begins shifting out the data after the 4th rising

after the next rising edge. The 4th rising clock edge

produces the MSB of the conversion at DOUT, and the

MSB remains valid 4ns after the 5th rising edge. Since

there are 12 data bits and 3 leading zeros, at least 16

rising clock edges are needed to shift out these bits.

For continuous operation, pull CNVST high between the

14th and the 16th SCLK rising edges. If CNVST stays

low after the falling edge of the 16th SCLK cycle, the

DOUT line goes to a high-impedance state on either

CNVST’s rising edge or the next SCLK’s rising edge.

1.5Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

10

______________________________________________________________________________________

DOUT

MODE

SCLK

CNVST

DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH

CONVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE

ONE 8-BIT TRANSFER

1ST SCLK RISING EDGE

PPD

00

0

D11

D10

D9

D8

D7

NORMAL

Figure 6. SPI Interface—Partial Power-Down Mode

Figure 5. Interface-Timing Sequence

CONTINUOUS-CONVERSION

SELECTION WINDOW

CNVST

DOUT

SCLK

414

12

8

3

16

HIGH IMPEDANCE

D1

D4

D6

D5

D9

D8

D7

D11

D10

POWER-MODE SELECTION WINDOW

D0

D2

D3