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M25P64-VMF6P Datasheet(PDF) 8 Page - STMicroelectronics |
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M25P64-VMF6P Datasheet(HTML) 8 Page - STMicroelectronics |
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8 / 38 page  M25P64 8/38 OPERATING FEATURES Page Programming To program one data byte, two instructions are re- quired: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which con- sists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be pro- grammed at a time (changing bits from 1 to 0), pro- vided that they lie in consecutive addresses on the same page of memory. Sector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration tSE or tBE). The Erase instruction must be preceded by a Write Enable (WREN) instruction. Polling During a Write, Program or Erase Cycle A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The Write In Progress (WIP) bit is provided in the Status Regis- ter so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is com- plete. Active Power and Standby Power Modes When Chip Select (S) is Low, the device is select- ed, and in the Active Power mode. When Chip Select (S) is High, the device is dese- lected, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Standby Power mode. The device consumption drops to ICC1. Status Register The Status Register contains a number of status and control bits that can be read or set (as appro- priate) by specific instructions. WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. WEL bit. The Write Enable Latch (WEL) bit indi- cates the status of the internal Write Enable Latch. BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. SRWD bit. The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits. |
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