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HM628128A Datasheet(PDF) 4 Page - Hitachi Semiconductor |
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HM628128A Datasheet(HTML) 4 Page - Hitachi Semiconductor |
4 / 13 page Block Diagram Function Table CS1 CS2 OE WE Mode VCC current I/O pin Ref. cycle H X X X Standby ISB, ISB1 High-Z — X L X X Standby ISB, ISB1 High-Z — L H H H Output disable ICC High-Z — L H L H Read ICC Dout Read cycle L H H L Write ICC Din Write cycle (1) L H L L Write ICC Din Write cycle (2) Note: X: H or L 4 HM628128A Series • • • • • • • • • • • I/O0 I/O7 CS2 WE OE A8 A9 A11 A0 A2 V V CC SS Row Decoder Memory Matrix 512 x 2,048 Column I/O Column Decoder Input Data Control Timing Pulse Generator Read/Write Control A1 A3 A13 A15 A6 A7 A12 A14 A16 A5 A4 CS1 A10 (MSB) (LSB) (LSB) (MSB) |
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