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FS6011-02 Datasheet(PDF) 1 Page - List of Unclassifed Manufacturers

Part No. FS6011-02
Description  DIGITAL AUDIO/VIDEO CLOCK GENERATOR IC
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  X T
July 1998
American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
7.20.98
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1.0
Features
Triple phase-locked loop (PLL) device provides exact
ratiometric derivation of Audio, Processor, and Utility
Clocks
On-chip tunable voltage-controlled crystal oscillator
(VCXO) allows precise system frequency tuning
Serial interface for Audio and Utility Clock frequency
selection
Board-programmable Processor Clock frequency
selection
Supports 32, 44.1, and 48kHz 256x oversampled
DACs as well as 384x at 44.1kHz and 512x at 48kHz
Tunable Audio Clock frequencies for undetectable
resynchronization of audio and video streams
Small circuit board footprint (16-pin 0.150
″ SOIC)
Custom frequency selections available - contact your
local AMI Sales Representative for more information
Figure 1: Block Diagram
VCXO
Serial
Interface
SDATA
SCLK
SLOAD
FS6011
UCLK
Processor
Clock PLL
Audio
Clock PLL
Utility
Clock PLL
XOUT
XIN
CLK_27
ACLK
PCLK
XTUNE
PSEL1
PSEL0
2.0
Description
The FS6011-02 is a monolithic CMOS clock generator IC
designed to minimize cost and component count in digital
video/audio systems.
At the core of the FS6011-02 is circuitry that implements
a voltage-controlled crystal oscillator when an external
resonator (nominally 27MHz) is attached. The VCXO al-
lows device frequencies to be precisely adjusted for use
in systems that have frequency matching requirements,
such as digital satellite receivers.
Three high-resolution phase-locked loops independently
generate three other selectable frequencies derived from
the VCXO frequency. These clock frequencies are re-
lated to the VCXO frequency and to each other by exact
ratios. The locking of all the output frequencies together
can eliminate unpredictable artifacts in video systems
and unpredictable electromagnetic interference (EMI)
performance due to frequency harmonic stacking.
Figure 2: Pin Configuration
1
16
2
3
4
5
6
7
8
15
14
13
12
11
10
9
SCLK
SDATA
SLOAD
VSS
XIN
XOUT
XTUNE
VDD
PSEL1
PSEL0
VSS
PCLK
UCLK
VDD
ACLK
CLK27
16-pin (0.150
″) SOIC




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