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FS6011-02 Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers

Part No. FS6011-02
Description  DIGITAL AUDIO/VIDEO CLOCK GENERATOR IC
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Maker  ETC [List of Unclassifed Manufacturers]
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  X T
July 1998
4
7.20.98
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4.1
Audio PLL Clock Frequencies (ACLK)
The ACLK frequency is controlled by register bits D[0],
D[1], and D[2] accessed via the serial interface. The
ACLK frequencies listed below are derived via the PLL
Divider Ratio from a reference frequency of 27MHz.
Table 3: ACLK Frequency Select
D[2]
D[1]
D[0]
PLL DIVIDER
RATIO
AUDIO
OVERSAMPLING
ACLK
(MHz)
0
0
0
1024 / 2250
48kHz x 256
12.288
0
0
1
1024 / 3375
32kHz x 256
8.192
0
1
0
1024 / 4500
48kHz x 256 / 2
6.144
0
1
1
1024 / 6750
32kHz x 256 / 2
4.096
1
0
0
1568 / 3750
44.1kHz x 256
11.2896
1
0
1
1568 / 2500
44.1kHz x 384
16.9344
1
1
0
1568 / 7500
44.1kHz x 256 / 2
5.6448
1
1
1
1024 / 1125
48kHz x 512
24.576
NOTE: Contact AMI for custom PLL frequencies
4.2
Audio Clock Off-Speed Frequencies
The ACLK frequencies shown may be smoothly modified
to a slightly higher or lower value under register control.
Register bit D[3] must be a logic-one to activate this
mode. The value of D[4] controls whether the frequency
will be adjusted slightly low (D[4] = 0) or high (D[4] = 1).
Table 4: Audio Off Speed Frequencies
D[4]
D[3]
D[2]
D[1]
D[0]
PLL DIVIDER
RATIO
ACLK
(MHz)
01000
1023 / 2250
12.276
01001
1023 / 3375
8.184
01010
1023 / 4500
6.138
01011
1023 / 6750
4.092
01100
1567 / 3750
11.2824
01101
1567 / 2500
16.9236
01110
1567 / 7500
5.6412
01111
1023 / 1125
24.5520
11000
1025 / 2250
12.3000
11001
1025 / 3375
8.2000
11010
1025 / 4500
6.1500
11011
1025 / 6750
4.1000
11100
1569 / 3750
11.2968
11101
1569 / 2500
16.9432
11110
1569 / 7500
5.6484
11111
1025 / 1125
24.6000
4.3
Utility PLL Clock Frequencies (UCLK)
The UCLK frequency is controlled by register bits D[5],
D[6] and D[7], accessed via the serial interface. UCLK
frequencies listed below are derived via the PLL Divider
Ratio from a reference frequency of 27MHz.
Table 5: UCLK Frequency Select
D[7]
D[6]
D[5]
PLL DIVIDER RATIO
UCLK (MHz)
0
0
0
16 / 27
16.0000
0
0
1
35 / 33
28.6363
0
1
0
1568 / 3750
11.2896
0
1
1
1
27.0000
1
0
0
544 / 375
39.1680
1
0
1
728 / 375
52.4160
1
1
0
10 / 9
30.0000
1
1
1
1024 / 1125
24.5760
NOTE: Contact AMI for custom PLL frequencies
4.4
Processor PLL Frequencies (PCLK)
The PCLK frequency is controlled by the logic levels on
the PSEL0 and PSEL1 inputs. These inputs have weak
pull-downs. PCLK frequencies listed below are derived
via the PLL Divider Ratio from a reference frequency of
27MHz.
Table 6: PCLK Frequency Select
PSEL1
PSEL0
PLL DIVIDER RATIO
PCLK (MHz)
0
0
32 / 27
32.0000
0
1
40 / 27
40.0000
1
0
50 / 27
50.0000
1
1
60 / 41
39.5122
NOTE: Contact AMI for custom PLL frequencies




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