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CY7C4282
CY7C4292
Document #: 38-06009 Rev. *B
Page 2 of 16
Selection Guide
7C4282/92-10
7C4282/92-15
7C4282/92-25
Unit
Maximum Frequency
100
66.7
40
MHz
Maximum Access Time
8
10
15
ns
Minimum Cycle Time
10
15
25
ns
Minimum Data or Enable Set-up
3
4
6
ns
Minimum Data or Enable Hold
0.5
1
1
ns
Maximum Flag Delay
8
10
15
ns
Active Power Supply Current (ICC)
Commercial
404040
mA
Industrial
45
CY7C4282
CY7C4292
Density
64k x 9
128k x 9
Package
64-pin 10x10 STQFP
64-pin 10x10 STQFP
Pin Configuration
STQFP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
16
CY7C4282
CY7C4292
WEN
RS
D8
D7
D6
N/C
N/C
N/C
N/C
N/C
N/C
D5
N/C
D2
D4
D3
Q5
Q4
GND
Q3
Q2
VCC
Q1
Q0
GND
N/C
FF
OE
EF
N/C
GND
FL/RT
Pin Definitions
Signal
Name
Description
I/O
Description
D0 − 8
Data Inputs
I
Data Inputs for 9-bit bus.
Q0 − 8
Data Outputs
O Data Outputs for 9-bit bus.
WEN
Write Enable
I
The only write enable when device is configured to have programmable flags. Data is
written on a LOW-to-HIGH transition of WCLK when WEN is asserted and FF is HIGH.
REN
Read Enable
I
Enables the device for Read operation. REN must be asserted LOW to allow a read
operation.
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full. When
LD is asserted, WCLK writes data into the programmable flag-offset register.
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