9 / 16 page
CY7C4282
CY7C4292
Document #: 38-06009 Rev. *B
Page 9 of 16
Switching Characteristics Over the Operating Range
Parameter
Description
7C4282/92-10
7C4282/92-15
7C4282/92-25
Unit
Min.
Max.
Min.
Max.
Min.
Max.
tS
Clock Cycle Frequency
100
66.7
40
MHz
tA
Data Access Time
2
8
2
10
2
15
ns
tCLK
Clock Cycle Time
10
15
25
ns
tCLKH
Clock HIGH Time
4.5
6
10
ns
tCLKL
Clock LOW Time
4.5
6
10
ns
tDS
Data Set-up Time
3
4
6
ns
tDH
Data Hold Time
0.5
1
1
ns
tENS
Enable Set-up Time
3
4
6
ns
tENH
Enable Hold Time
0.5
1
1
ns
tRS
Reset Pulse Width[12]
10
15
25
ns
tRSS
Reset Set-up Time
8
10
15
ns
tRSR
Reset Recovery Time
8
10
15
ns
tRSF
Reset to Flag and Output Time
10
15
25
ns
tPRT
Retransmit Pulse Width
60
60
60
ns
tRTR
Retransmit Recovery Time
90
90
90
ns
tOLZ
Output Enable to Output in Low Z[13]
00
0
ns
tOE
Output Enable to Output Valid
3738
3
12
ns
tOHZ
Output Enable to Output in High Z[13]
3738
3
12
ns
tWFF
Write Clock to Full Flag
8
10
15
ns
tREF
Read Clock to Empty Flag
8
10
15
ns
tPAF
Clock to Programmable Almost-Full Flag
8
10
15
ns
tPAE
Clock to Programmable Almost-Full Flag
8
10
15
ns
tSKEW1
Skew Time between Read Clock and Write Clock
for Empty Flag and Full Flag
56
10
ns
tSKEW2
Skew Time between Read Clock and Write Clock
for Almost-Empty Flag and Almost-Full Flag
10
15
18
ns
Notes:
12. Pulse widths less than minimum values are not allowed.
13. Values guaranteed by design, not currently tested.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
