CY7C1350F
Document #: 38-05305 Rev. *A
Page 10 of 16
Switching Characteristics Over the Operating Range[17, 18]
250 MHz
225 MHz
200 MHz
166 MHz
133 MHz
100 MHz
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tPOWER
VDD (typical) to the first
Access[13]
1
1
1
1
11
ms
Clock
tCYC
Clock Cycle Time
4.0
4.4
5.0
6.0
7.5
10
ns
tCH
Clock HIGH
1.7
2.0
2.0
2.5
3.0
3.5
ns
tCL
Clock LOW
1.7
2.0
2.0
2.5
3.0
3.5
ns
Output Times
tCO
Data Output Valid After CLK
Rise
2.6
2.6
2.8
3.5
4.0
4.5
ns
tDOH
Data Output Hold After CLK
Rise
1.0
1.0
1.0
2.0
2.0
2.0
ns
tCLZ
Clock to Low-Z[14, 15, 16]
0
0
0
0
0
0
ns
tCHZ
Clock to High-Z[14, 15, 16]
2.6
2.6
2.8
3.5
4.0
4.5
ns
tOEV
OE LOW to Output Valid
2.6
2.6
2.8
3.5
4.0
4.5
ns
tOELZ
OE LOW to Output
Low-Z[14, 15, 16]
0
0
0
0
0
0
ns
tOEHZ
OE HIGH to Output
High-Z[14, 15, 16]
2.6
2.6
2.8
3.5
4.0
4.5
ns
Set-up Times
tAS
Address Set-up Before CLK
Rise
0.8
1.2
1.2
1.5
1.5
1.5
ns
tALS
ADV/LD Set-up Before CLK
Rise
0.8
1.2
1.2
1.5
1.5
1.5
ns
tWES
GW, BW[A:D] Set-Up Before
CLK Rise
0.8
1.2
1.2
1.5
1.5
1.5
ns
tCENS
CEN Set-up Before CLK Rise
0.8
1.2
1.2
1.5
1.5
1.5
ns
tDS
Data Input Set-up Before CLK
Rise
0.8
1.2
1.2
1.5
1.5
1.5
ns
tCES
Chip Enable Set-Up Before
CLK Rise
0.8
1.2
1.2
1.5
1.5
1.5
ns
Hold Times
tAH
Address Hold After CLK Rise
0.4
0.5
0.5
0.5
0.5
0.5
ns
tALH
ADV/LD Hold after CLK Rise
0.4
0.5
0.5
0.5
0.5
0.5
ns
tWEH
GW, BW[A:D] Hold After CLK
Rise
0.4
0.5
0.5
0.5
0.5
0.5
ns
tCENH
CEN Hold After CLK Rise
0.4
0.5
0.5
0.5
0.5
0.5
ns
tDH
Data Input Hold After CLK Rise 0.4
0.5
0.5
0.5
0.5
0.5
ns
tCEH
Chip Enable Hold After CLK
Rise
0.4
0.5
0.5
0.5
0.5
0.5
ns
Shaded areas contain advance information.
Notes:
13. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a Read or Write operation
can be initiated.
14. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
15. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve Three-state prior to Low-Z under the same system conditions
16. This parameter is sampled and not 100% tested.
17. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
18. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
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