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APL5332KAC-TRL Datasheet(PDF) 10 Page - Anpec Electronics Coropration |
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APL5332KAC-TRL Datasheet(HTML) 10 Page - Anpec Electronics Coropration |
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10 / 17 page  Copyright ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 APL5332 www.anpec.com.tw 10 Application Information Layout and Thermal Consideration The input capacitors are normally placed near VIN for good performances. Ceramic decoupling capacitors for load must be placed as close to the load to re- duce the parasitic inductors of traces. It is also rec- ommended that the APL5332 and output capacitors are placed near the load for good load regulation and transient response. The negative pins of the input and output capacitors and the GND pin of the APL5332 are connected to analog ground plane of the load. See Figure 1. The SOP-8-P is a cost-effective pack- age featuring a small size as a standard SOP-8 and a bottom thermal pad to minimize the thermal resis- tance of the package, being applicable to high cur- rent applications. The thermal pad of SOP-8-P or TO- 252-5 is soldered to the top ground pad which is con- nected to the internal or bottom ground plane by sev- eral vias. The printed circuit board (PCB) forms a heat sink and dissipates major heat into ambient air. Thermal resistance consists of two main elements, θ JC (junction-to-case thermal resistance) and θCA (case- to-ambient thermal resistance). θJC is specified from the IC junction to the bottom of the thermal pad di- rectly below the die. θCA is the resistance from the bottom of thermal pad to the ambient air and it in- cludes θCS (case-to-sink thermal resistance) and (sink- to-ambient thermal resistance). The specified path for heat flow is the lowest resistance path and it dissipates major heat to the ambient air. Normally θCA is major re- sistance in the path. Enlarging the internal or bottom ground plane reduces the resistance θCA . The relation- ship between power dissipation and temperatures is PD = (TJ - TA) / θJA where, PD : power dissipation TJ : Junction Temperature TA : Ambient Temperature θ JA : Junction-to-Ambient Thermal Resistance T herm al pad Die Top ground pad Printed circuit board Internal ground plane Vias Ambient Air 118 mil 102 mil SO P-8-P Figure 1 Figure 2 shows a recommended board layout using the SOP-8-P package. An area of 140mil*110mil on the top layer (250mil*250mil) is used as a thermal pad for APL5332 and is connected to the internal or bottom ground plane by vias. The vias shold have proper hole size to retain solder, and help heat conduction. More area of the internal or bottom plane reduces θJA and is better for dissipating power. The recommended area is without limit. Therefore the PCB and all com- ponents form a heat sink. 250m il 140m il Internal or bottom Ground plane T op layer gr ound plane Solder ing ar ea for bottom pad Pad Vias 12 34 8 76 5 Figure 2 |
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