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M95320-WDW6TG Datasheet(PDF) 7 Page - STMicroelectronics |
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M95320-WDW6TG Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 39 page 7/39 M95640, M95320 CONNECTING TO THE SPI BUS These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes Low. All output data bytes are shifted out of the device, most significant bit first. The Serial Data Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register in- structions) have been clocked into the device. Figure 5 shows three devices, connected to an MCU, on a SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the others being high impedance. Figure 5. Bus Master and Memory Devices on the SPI Bus Note: 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate. SPI Modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: – CPOL=0, CPHA=0 – CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 6, is the clock polarity when the bus mas- ter is in Stand-by mode and not transferring data: – C remains at 0 for (CPOL=0, CPHA=0) – C remains at 1 for (CPOL=1, CPHA=1) AI03746D Bus Master (ST6, ST7, ST9, ST10, Others) SPI Memory Device SDO SDI SCK CQD S SPI Memory Device CQD S SPI Memory Device CQD S CS3 CS2 CS1 SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) W HOLD W HOLD W HOLD |
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