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M95128-MN3TG Datasheet(PDF) 5 Page - STMicroelectronics |
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M95128-MN3TG Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 39 page 5/39 M95256, M95128 SUMMARY DESCRIPTION These electrically erasable programmable memo- ry (EEPROM) devices are accessed by a high speed SPI-compatible bus. The memory array is organized as 32768 x 8 bit (M95256) and 16384 x 8 bit (M95128). The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 2. and Figure 2.. The device is selected when Chip Select (S) is tak- en Low. Communications with the device can be interrupted using Hold (HOLD). Figure 2. Logic Diagram Figure 3. DIP, SO and TSSOP Connections Note: See PACKAGE MECHANICAL section for package dimen- sions, and how to identify pin-1. Table 2. Signal Names AI01789C S VCC M95xxx HOLD VSS W Q C D C Serial Clock D Serial Data Input Q Serial Data Output S Chip Select W Write Protect HOLD Hold VCC Supply Voltage VSS Ground D VSS C HOLD Q SVCC W AI01790D M95xxx 1 2 3 4 8 7 6 5 |
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