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MT9V024 Datasheet(PDF) 16 Page - ON Semiconductor |
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MT9V024 Datasheet(HTML) 16 Page - ON Semiconductor |
16 / 40 page MT9V024/D www.onsemi.com 16 tSF2SF tSFW tFV2E tSF2FV tE2SF tEW tE2LED tSF2LED EXPOSURE TIME EXPOSURE STFRM_OUT STLN_OUT FRAME_VALID LINE_VALID LED_OUT Figure 20. Exposure and Readout Timing (Sequential Mode) NOTES: 1. Not drawn to scale. 2. Frame readout shortened for clarity 3. STLN_OUT pulses are optional during exposure time. 4. Sequential progressive scan readout mode shown. Signal Path The MT9V024 signal path consists of a programmable gain, a programmable analog offset, and a 10−bit ADC. See “Black Level Calibration” for the programmable offset operation description. Figure 21. Signal Path Pixel Output (reset minus signal) Offset Correction Voltage (R0x48 or result of BLC) Gain Selection (R0x35 or R0x36 or result of AGC) ADC Data (9:0) 10 (12) bit ADC C1 C2 + Σ × VREF (R0x2C) ON−CHIP BIASES ADC Voltage Reference The ADC voltage reference is programmed through R0x2C, bits 2:0. The ADC reference ranges from 1.0 V to 2.1 V. The default value is 1.4 V. The increment size of the voltage reference is 0.1 V from 1.0 V to 1.6 V (R0x2C[2:0] values 0 to 6). At R0x2C[2:0] = 7, the reference voltage jumps to 2.1 V. It is very important to preserve the correct values of the other bits in R0x2C. The default register setting is 0x0004. This corresponds to 1.4 V−at this setting 1 mV input to the ADC equals approximately 1 LSB. V_Step Voltage Reference This voltage is used for pixel high dynamic range operations, programmable from R0x31 through R0x34 for context A, or R0x39 through R0x3B for context B. Chip Version Chip version register R0x00 is read−only. WINDOW CONTROL Registers column start A/B, row start A/B, window height A/B (row size), and window width (column size) A/B control the size and starting coordinates of the window. |
Similar Part No. - MT9V024_17 |
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Similar Description - MT9V024_17 |
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