XRT7300

E3/DS3/STS-1 LINE INTERFACE UNIT

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REV. 1.1.1

II

2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY ......................................................................... 21

2.3 THE HDB3/B3ZS ENCODER BLOCK........................................................................................................ 22

B3ZS Encoding .................................................................................................................................... 22

Figure 13.An Example of B3ZS Encoding ........................................................................................................ 22

HDB3 Encoding.................................................................................................................................... 22

Figure 14.An Example of HDB3 Encoding ........................................................................................................ 23

Enabling/Disabling the HDB3/B3ZS Encoder ...................................................................................... 23

2.4 THE TRANSMIT PULSE SHAPER CIRCUITRY .............................................................................................. 23

COMMAND REGISTER CR2 (ADDRESS = 0X02 .................................................................................... 23

Enabling the Transmit Line Build-Out Circuit ....................................................................................... 23

Disabling the Transmit Line Build-Out Circuit ...................................................................................... 23

COMMAND REGISTER CR1 (ADDRESS = 0X01) ................................................................................... 23

Design Guideline for Setting the Transmit Line Build-Out Circuit ........................................................ 24

COMMAND REGISTER CR1 (ADDRESS = 0X01) ................................................................................... 24

The Transmit Line Build-Out Circuit and E3 Applications .................................................................... 24

2.5 INTERFACING THE TRANSMIT SECTION OF THE XRT7300 TO THE LINE ..................................................... 24

Figure 15.Recommended Schematic for Interfacing the Transmit Section of the XRT7300 to the Line...........24

TRANSFORMER RECOMMENDATIONS ........................................................................................................ 25

3.0 THE RECEIVE SECTION ......................................................................................................................... 25

3.1 INTERFACING THE RECEIVE SECTION OF THE XRT7300 TO THE LINE ....................................................... 25

Figure 16.Recommended Schematic for Interfacing the Receive Section of the XRT7300 to the Line (Transform-

er-Coupling) ........................................................................................................................................ 26

Figure 17.Recommended Schematic for Interfacing the Receive Section of the XRT7300 to the Line (Capaci-

tive-Coupling)...................................................................................................................................... 26

3.2 THE RECEIVE EQUALIZER BLOCK ............................................................................................................26

Figure 18. The Typical Application for the System Installer .............................................................................. 27

COMMAND REGISTER CR2 (ADDRESS = 0X02) ................................................................................... 28

3.3 PEAK DETECTOR AND SLICER ................................................................................................................. 28

3.4 CLOCK RECOVERY PLL .......................................................................................................................... 28

3.5 THE HDB3/B3ZS DECODER ...................................................................................................................28

B3ZS Decoding DS3/STS-1 Applications ............................................................................................29

Figure 19.An Example of B3ZS Decoding ........................................................................................................ 29

HDB3 Decoding E3 Applications.......................................................................................................... 29

Figure 20.An Example of HDB3 Decoding........................................................................................................ 29

Enabling/Disabling the HDB3/B3ZS Decoder ...................................................................................... 30

3.6 LOS DECLARATION/CLEARANCE ............................................................................................................. 30

COMMAND REGISTER CR2 (ADDRESS = 0X02) ................................................................................... 30

The LOS Declaration/Clearance Criteria for E3 Applications...............................................................30

Figure 21.The Signal Levels that the XRT7300 Declares and Clears LOS (E3 Mode Only) ............................ 31

Figure 22.The Behavior the LOS Output Indicator In Response to the Loss of Signal and the Restoration of Sig-

nal ....................................................................................................................................................... 31

The LOS Declaration/Clearance Criteria for DS3 and STS-1 Applications.......................................... 32

Table 4:The ALOS Declaration and Clearance Thresholds for a Given Setting of LOSTHR (DS3 and STS-1 Ap-

plications) for Equalizer Enabled or Disabled ...................................................................................... 32

COMMAND REGISTER CR0 (ADDRESS = 0X00) ................................................................................... 32

COMMAND REGISTER CR2 (ADDRESS = 0X02) ................................................................................... 33

COMMAND REGISTER CR0 (ADDRESS = 0X00) ................................................................................... 33