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LT5506EUF Datasheet(PDF) 3 Page - Linear Technology |
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LT5506EUF Datasheet(HTML) 3 Page - Linear Technology |
3 / 12 page LT5506 3 5506fa VCC = 3V. f2×LO = 570MHz, P2×LO = –5dBm (Note 5), fIF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3) ELECTRICAL CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Specifications over the –40 °C to 85°C temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Tests are performed as shown in the configuration of Figure 6. The IF input transformer loss is substracted from the measured values. Note 4: Power gain is defined here as the I (or Q) output power into a 4k Ω differential load, divided by the IF input power in dB. To calculate the voltage gain between the differential I output (or Q output) and the IF input, including ideal matching network, 10 • log(4k Ω/50) = 19dB has to be added to this power gain. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Variable Gain Amplifier (VGA) Gain Slope Linearity Error VCTRL = 0V to 1.4V ±0.5 dB Temperature Gain Shift T = –40 °C to 85°C, VCTRL = 0V to 1.4V ±0.3 dB Gain Control Response Time Settled within 10% of Final Value 100 ns Gain Control Voltage Range 0 to 1.7 V Gain Control Slope 43 dB/V Gain Control Input Impedance To Internal 0.2V 25 k Ω Delay Shift Over Gain Control Measured Over 10dB Step 2 ps/dB Baseband Lowpass Filter –3dB Cutoff Frequency 7.2 8.8 10.4 MHz Group Delay Ripple 5ns 2xLO Input f2xLO Frequency Range 80 to 1000 MHz P2xLO Input Power 1:2 Transformer with 240 Ω Shunt Resistor (Note 5) –20 –5 dBm Input Power LC Balun (Note 5) –10 dBm Input Impedance Differential Between 2xLO+ and 2xLO– 800 Ω//0.4pF DC Common Mode Voltage VCC – 0.4 V IF Detector IF Detector Range Referred to IF Input –30 to 8 dBm Output Voltage Range For PIF = –30dBm to 8dBm 0.3 to 1.2 V Detector Response Time With External 1.8pF Load, 100 ns Settling within 10% of Final Value Power Supply VCC Supply Voltage 1.8 5.25 V ICC Supply Current EN = High, STBY = Low or High 26.5 36 mA IOFF Shutdown Current EN, STBY < 350mV 0.2 30 µA ISTBY Standby Current EN = Low; STBY = High 3.6 5.5 mA Mode Enable Enable Pin Voltage EN = High 1 V Disable Enable Pin Voltage EN = Low 0.5 V Standby Standby Pin Voltage STBY = High 1 V No Standby Standby Pin Voltage STBY = Low 0.5 V Note 5: If a narrow-band match is used in the 2xLO path instead of a 1:2 transformer with 240 Ω shunt resistor, 2xLO input power can be reduced to –10dBm, without degrading the phase imbalance. See Figure 11 and Figure 6. Note 6: Differential between IOUT + and IOUT– (or differential between QOUT+ and QOUT–). Note 7: The gain control voltage VCTRL is set in such a way that the differential output voltage between IOUT+ and IOUT– (or differential between QOUT+ and QOUT–) is 800mVP-P, with the given input power PIF. Note 8: The typical parameter is defined as the mean of the absolute values of the data distribution. |
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