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AR0542 Datasheet(PDF) 8 Page - ON Semiconductor |
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AR0542 Datasheet(HTML) 8 Page - ON Semiconductor |
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8 / 55 page  AR0542 www.onsemi.com 8 OUTPUT DATA FORMAT Parallel Pixel Data Interface AR0542 image data is read out in a progressive scan. Valid image data is surrounded by horizontal blanking and vertical blanking, as shown in Figure 5. The amount of horizontal blanking and vertical blanking is programmable; LV is HIGH during the shaded region of the figure. FV timing is described in the “Output Data Timing (Parallel Pixel Data Interface)”. Figure 5. Spatial Illustration of Image Readout ..................................... ..................................... 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 ................................. ................................. 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VALID IMAGE HORIZONTAL BLANKING 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 VERTICAL BLANKING VERTICAL/HORIZONTAL BLANKING P0,0 P0,1 P0,2 P1,0 P1,1 P1,2 P0,n−1 P0,n P1,n−1 P1,n Pm−1,0 Pm−1,1 Pm,0 Pm,1 Pm−1,n−1 Pm−1,n Pm,n−1 Pm,n Output Data Timing (Parallel Pixel Data Interface) AR0542 output data is synchronized with the PIXCLK output. When LV is HIGH, one pixel value is output on the 10−bit DOUT output every PIXCLK period. The pixel clock frequency can be determined based on the sensor’s master input clock and internal PLL configuration. The rising edges on the PIXCLK signal occurs one−half of a pixel clock period after transitions on LV, FV, and DOUT (see Figure 6). This allows PIXCLK to be used as a clock to sample the data. PIXCLK is continuously enabled, even during the blanking period. The AR0542 can be programmed to delay the PIXCLK edge relative to the DOUT transitions. This can be achieved by programming the corresponding bits in the row_speed register. The parameters P, A, and Q in Figure 7 are defined in Table 4. Figure 6. Pixel Data Timing Example P0[9:0] P1 P2 P3 P4 P5n−2 Pn−1 Pn Valid Image Data Blanking Blanking LV PIXCLK DOUT[11:0] P [9:0] [9:0] [9:0] [9:0] [9:0] [9:0] |
Similar Part No. - AR0542_17 |
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Similar Description - AR0542_17 |
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