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AR0330CM Datasheet(PDF) 25 Page - ON Semiconductor |
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AR0330CM Datasheet(HTML) 25 Page - ON Semiconductor |
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25 / 53 page  AR0330CM www.onsemi.com 25 PIXEL OUTPUT INTERFACES Parallel Interface The parallel pixel data interface uses these output-only signals: • FV • LV • PIXCLK • DOUT[11:0] The parallel pixel data interface is disabled by default at power up and after reset. It can be enabled by programming R0x301A. Table 30 shows the recommended settings. When the parallel pixel data interface is in use, the serial data output signals can be left unconnected. Set reset_register[12] to disable the serializer while in parallel output mode. Output Enable Control When the parallel pixel data interface is enabled, its signals can be switched asynchronously between the driven and High−Z under pin or register control, as shown in Table 29. OE_BAR pin is only available on the bare die version. Table 29. OUTPUT ENABLE CONTROL OE_BAR Pin Drive Signals R0x301A−B[6] Description Disabled 0 Interface High−Z Disabled 1 Interface Driven 1 0 Interface High−Z X 1 Interface Driven 0 X Interface Driven Configuration of the Pixel Data Interface Fields in R0x301A are used to configure the operation of the pixel data interface. The supported combinations are shown in Table 30. Table 30. CONFIGURATION OF THE PIXEL DATA INTERFACE Serializer Disable R0x301A−B[12] Parallel Enable R0x301A−B[7] Standby End-of-Frame R0x301A−B[7] Description 0 0 1 Power up default. Serial pixel data interface and its clocks are enabled. Transitions to soft standby are synchronized to the end of frames on the serial pixel data interface. 1 1 0 Parallel pixel data interface, sensor core data output. Serial pixel data interface and its clocks disabled to save power. Transitions to soft standby are synchronized to the end of the current row readout on the parallel pixel data interface. 1 1 1 Parallel pixel data interface, sensor core data output. Serial pixel data interface and its clocks disabled to save power. Transitions to soft standby are synchronized to the end of frames in the parallel pixel data interface. High Speed Serial Pixel Data Interface The High Speed Serial Pixel (HiSPi) interface uses four data and one clock low voltage differential signaling (LVDS) outputs. • SLVSC_P • SLVSC_N • SLVS0_P • SLVS0_N • SLVS1_P • SLVS1_N • SLVS2_P • SLVS2_N • SLVS3_P • SLVS3_N The HiSPi interface supports three protocols, Streaming S, Streaming SP, and Packetized SP. The streaming protocols conform to a standard video application where each line of active or intra-frame blanking provided by the sensor is transmitted at the same length. The Packetized SP protocol will transmit only the active data ignoring line-to-line and frame-to-frame blanking data. These protocols are further described in the High-Speed Serial Pixel (HiSPi) Interface Protocol Specification V1.00.00. The HiSPi interface building block is a unidirectional differential serial interface with four data and one double data rate (DDR) clock lanes. One clock for every four serial data lanes is provided for phase alignment across multiple lanes. Figure 21 shows the configuration between the HiSPi transmitter and the receiver. |
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