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ICS87608AYIT Datasheet(PDF) 8 Page - List of Unclassifed Manufacturers |
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8 / 12 page 87608AYI www.icst.com/products/hiperclocks.html REV. B MARCH 11, 2005 8 Integrated Circuit Systems, Inc. ICS87608I LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR APPLICATION INFORMATION As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87608I provides sepa- rate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD, VDDA, and VDDOX should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 Ω resistor along with a 10µF and a .01μF bypass capacitor should be connected to each V DDA. POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING 10 Ω V DDA 10 μF .01 μF 3.3V .01 μF V DD CRYSTAL INPUT INTERFACE The ICS87608I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel Figure 2. CRYSTAL INPUt INTERFACE resonant crystal and were chosen to minimize the frequency ppm error. The optimum C1 and C2 values can be slightly ad- justed for optimum frequency accuracy. C1 22p X1 18pF Parallel Cry stal C2 22p XTAL2 XTAL1 |
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