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H6061258P Datasheet(PDF) 2 Page - EM Microelectronic - MARIN SA |
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H6061258P Datasheet(HTML) 2 Page - EM Microelectronic - MARIN SA |
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2 / 8 page  R H6061 Copyright © 2004, EM Microelectronic-Marin SA 2 www.emmicroelectronic.com Absolute Maximum Ratings Parameter Symbol Conditions Voltage VDD to VSS VDD − 0.3 to + 5.6 V Voltage at any pin to VSS VMIN − 0.3 Voltage at any pin to VDD VMAX + 0.3 Voltage at VIN to VSS VINMAX + 12 V Current at any output IMAX ± 10 mA Storage temperature TSTO -65°C to +150°C Electrostatic discharge max. to MIL-STD-833C method 3014 VSmax 1000V Table 1 Stresses above these listed maximum ratings may cause permanent damages to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. Handling Procedures This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the voltage range. Unused inputs must always be tied to a defined logic voltage level. Operating Conditions Parameter Symbol Min. Max. Units Operating temperature Industrial TAI -40 +85 °C Supply voltage VDD 2.7 5.25 V Version 11,12 VIN 0 12 V RC-oscillator programming External capacitance∗ C1 1 µF External resistance R1 10 k Ω * Leakage < 1 µA Table 2 Electrical Characteristics VDD = 5.0 V, TA = −40 to +85 °C, unless otherwise specified Parameter Symbol Test Conditions Min. Typ. Max. Units VDD activation threshold VDD deactivation threshold Supply current Input VIN, TCL Leakage current VON VOFF IDD IP TA = 25 °C TA = 25 °C RC open, TCL at VDD or VSS VSS < VIP <VDD TA = 80 °C 2.3 VON-0.3 80 0.005 2.7 140 1 V V µA µA TCL input low level TCL input high level Leakage on pins SAVE , RES , RES VIL VIH IOLK VOUT = VDD 2.4 0.050 0.8 1 V V µA O/P drive logic low IOL IOL IOL VOL = 0.4 V VDD = 3.5 V; VOL = 0.4 V VDD = 1.6 V; VOL = 0.4 V 4 2 80 8 mA mA µA Table 3 VIN Surveillance Voltage thresholds at TA = 25 °C Version No. Thresholds VSH VSL VRL at VDD Threshold Voltage Tolerance Threshold Ratio* Pin VIN Input 25 1.54 1.50 1.46 2.7 – 5.0 V ±10% ±2% ∼100 MΩ * Threshold ratio defined as VSH / VSL or VSL / VRL. Table 4 Timing Characteristics VDD = 5.0 V, TA = −40 °C to +85 °C, unless otherwise specified Parameter Symbol Test Conditions Min. Typ. Max. Units Propagation delays TCL to output pins TDIDO 250 500 ns VIN to output pins T AIDO Excluding debounce time TDB 4 10 µs Logic transition times on all output pins T TR Load 10 k Ω, 100 pF 30 100 ns Timeout period TTO RC open, unshielded, TA = 25 °C 60 100 160 ms TTCL input pulse width T TCL 150 ns Power-on reset debounce TDB TTO/64 ms Fastest pulse VIN with debounce TVINL -40 to +85 °C 10 µs Table 5 |
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