CY29352AIT datasheet(5/8 Pages) CYPRESS

Part #	CY29352AIT

Description	2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY29352

Document #: 38-07476 Rev. **

Page 5 of 8

AC Parameters[6] (VDD = 3.3V ± 5%, TA = –40°C to +85°C)

Parameter

Description

Condition

Min.

Typ.

Max.

Unit

fVCO

VCO Frequency

200

500

MHz

fin

Input Frequency

÷2 Feedback

100

200

MHz

÷4 Feedback

50

125

÷6 Feedback

33.33

83.33

÷8 Feedback

25

62.5

÷12 Feedback

16.67

41.67

Bypass mode (PLL_EN# = 1)

0

200

frefDC

Input Duty Cycle

25

75

%

tr , tf

TCLK Input Rise/FallTime

0.8V to 2.0V

1.0

ns

fMAX

Maximum Output Frequency

÷2 Output

100

200

MHz

÷4 Output

50

125

÷6 Output

33.33

83.33

÷8 Output

25

62.5

÷12 Output

16.67

41.67

DC

Output Duty Cycle

fMAX < 100 MHz

48

52

%

fMAX > 100 MHz

44

56

tr , tf

Output Rise/Fall times

0.55V to 2.4V

0.1

1.0

ns

t(φ)

Propagation Delay (static phase

offset)

TCLK to FB_IN, same VDD,

does not include jitter

–100

200

ps

tsk(O)

Output-to-Output Skew

Skew within each Bank

125

ps

tsk(B)

Bank-to-Bank Skew

Banks at same voltage, same

frequency

175

ps

Banks at same voltage,

different frequency

235

Banks at different voltage

425

tPLZ, HZ

Output Disable Time

8

ns

tPZL, ZH

Output Enable Time

10

ns

BW

PLL Closed Loop Bandwidth (-3dB)

÷2 Feedback

2

MHz

÷4 Feedback

1 – 1.5

÷6 Feedback

0.6

÷8 Feedback

0.75

÷12 Feedback

0.5

tJIT(CC)

Cycle-to-Cycle Jitter

Same frequency

100

ps

Multiple frequencies

275

tJIT(PER)

Period Jitter

Same frequency

100

ps

Multiple frequencies

150

tJIT(φ)

I/O Phase Jitter

VCO < 300 MHz

150

ps

VCO > 300 MHz

100

tLOCK

Maximum PLL Lock Time

1

ms

Note:

6.

AC characteristics apply for parallel output termination of 50

Ω to V

TT. Outputs are at the same supply voltage unless otherwise stated. Parameters are

guaranteed by characterization and are not 100% tested.

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