M1010-01 Datasheet Rev 0.4

2 of 8

Revised 29Sep2003

Integr ate d Circuit Systems , In c. ● Comm unication s Modules ● www.icst.com ● tel (508) 852-5400

Integrated

Circuit

Systems, Inc.

M1010-01

Preliminar y In f o r m atio n

Figure 3: Detailed Block Diagram

Number

Name

I/O

Configuration

Description

1, 2, 3, 10, 14, 26

GND

Ground

Power supply ground connections.

4

9

OP_IN

nOP_IN

Input

External loop filter connections.

See Figure 4, External Loop Filter, on pg. 4.

5

8

nOP_OUT

OP_OUT

Output

6

7

nVC

VC

Input

11, 18, 19, 33

VCC

Power

12, 13, 17, 25, 32

NC

No internal connection.

15

16

FOUT

nFOUT

Output

No internal terminator

Clock output pairs. Differential LVPECL.

20

nDIF_REF1

Input

Note 1: For typical values of internal pull-down and pull-up resistors, see “Inputs with Pull-down” and “Inputs with Pull-up”

in Table 8, DC Characteristics, on pg. 6.

Reference clock input pair.

Differential LVPECL or LVDS.

21

DIF_REF1

22

REF_SEL

Input

Reference clock input selection. LVCMOS/LVTTL:

23

nDIF_REF0

Input

Reference clock input pair.

Differential LVPECL or LVDS.

24

DIF_REF0

27

28

FIN_SEL1

FIN_SEL0

Input

I

nput clock frequency selection. LVCMOS/LVTTL.

(LUT) on pg. 3.

29

30

31

SEL0

SEL1

SEL2

Input

M and R divider value selection. LVCMOS/ LVTTL.

34, 35, 36

DNC

Do Not Connect.

Table 2: Pin Descriptions

Phase

Locked

Loop

(PLL)

M1010

SAW Delay Line

Phase

Shifter

VCSO

C

POST

C

POST

VC

nVC

R

POST

nOP_OUT

OP_OUT

R

POST

R

LOOP

R

LOOP

C

LOOP

C

LOOP

R

IN

R

IN

OP_IN

nOP_IN

Phase

Detector

Loop Filter

Amplifier

External

Loop Filter

Components

FOUT

nFOUT

SEL2:0

FIN_SEL1:0

R Div

MUX

0

REF_SEL

DIF_REF1

nDIF_REF1

DIF_REF0

nDIF_REF0

1

2

Divider LUT

3

Mfin Divider

LUT

Mfin Divider

M Div