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73K324BL-IGT Datasheet(PDF) 9 Page - List of Unclassifed Manufacturers |
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73K324BL-IGT Datasheet(HTML) 9 Page - List of Unclassifed Manufacturers |
9 / 34 page 73K324BL V.22bis/V.22/V.21/V.23 Bell 212A Single-Chip Modem w/Integrated Hybrid 9 REGISTER DESCRIPTIONS Eight 8-bit internal registers are accessible for control and status monitoring. The registers are accessed in read or write operations by addressing the AD0, AD1 and AD2 lines in serial mode, or in parallel mode. The address lines and CS are latched by ALE in the parallel mode. Register CR0 controls the method by which data is transferred over the phone line. CR1 controls the interface between the microprocessor and the 73K324BL internal state. DR is a detect register which provides an indication of monitored modem status conditions. TR, the tone control register, controls the DTMF generator, answer and guard tones and RXD output gate used in the modem initial connect sequence. CR2 is the primary DSP control interface and CR3 controls transmit attenuation and receive gain adjustments. All registers are read/write except for DR and ID which are read only. Register control and status bits are identified below: REGISTER BIT SUMMARY ADDRESS REGISTER AD-A0 D7 D6 D5 D4 D3 D2 D1 D0 CONTROL REGISTER 0 CR0 000 MODULATION OPTION MODULATION TYPE 1 MODULATION TYPE 0 TRANSMIT MODE 2 TRANSMIT MODE 1 TRANSMIT MODE 0 TRANSMIT ENABLE ANSWER/ ORIGINATE CONTROL REGISTER 1 CR1 001 TRANSMIT PATTERN 1 TRANSMIT PATTERN 0 ENABLE DETECT INTERRUPT BYPASS SCRAMBLER CLK CONTROL RESET TEST MODE 1 TEST MODE 0 DETECT REGISTER DR 010 RECEIVE LEVEL PATTERN S1 DET RECEIVE DATA UNSCR. MARK DETECT CARRIER DETECT SPECIAL TONE DETECT CALL PROGRESS DETECT SIGNAL QUALITY TONE CONTROL REGISTER TR 011 RXD OUTPUT CONTROL TRANSMIT GUARD TONE TRANSMIT ANSWER TONE TRANSMIT DTMF DTMF 3 DTMF2/ 4W/FDX DTMF1/ EXTENDED OVERSPEED DTMF0/ GUARD/ ANSWER CONTROL REGISTER 2 CR2 100 0 SPECIAL REGISTER ACCESS CALL INITIALIZE TRANSMIT S1 16 WAY RESET DSP TRAIN INHIBIT EQUALIZER ENABLE CONTROL REGISTER 3 CR3 101 TXDALT TRISTATE TX/RXCLK OH RECEIVE GAIN BOOST TRANSMIT ATTEN. 3 TRANSMIT ATTEN. 2 TRANSMIT ATTEN. 1 TRANSMIT ATTEN. 0 SPECIAL REGISTER SR 101 0 TX BAUD CLOCK RX UNSCR. DATA 0 TXD SOURCE SQ SELECT 1 SQ SELECT 0 0 ID REGISTER ID 110 ID ID ID ID X X X 1 NOTE: When a register containing reserved control bit is written into, the reserved bits must be programmed as 0’s. X = Undefined, mask in software |
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