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1 / 24 page Preliminary Rev. 0.6 6/01 Copyright © 2001 by Silicon Laboratories Si5311-DS06 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si5311 PRECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR IC Features Complete precision high speed clock multiplier and regenerator device: Applications Description The Si5311 is a fully integrated high-speed clock multiplier and clock regenerator IC. The clock multiplier generates an output clock that is an integer multiple of the input clock. When the clock multiplier is operating in either the 150–167 MHz range or the 600–668 MHz range, the clock regenerator operates simultaneously. The clock regenerator creates a “clean” version of the input clock by using the clock synthesis phase- locked loop (PLL) to remove unwanted jitter and square up the input clock’s rising and falling edges. The Si5311 uses Silicon Laboratories patented DSPLL™ architecture to achieve superior jitter performance while eliminating the analog loop filter found in traditional PLL designs. The Si5311 represents a new standard in low jitter, small size, low power, and ease-of-use for high speed clock devices. It operates from a single 2.5 V supply over the industrial temperature range (–40°C to 85°C). Functional Block Diagram ! Performs Clock Multiplication to One of Four Frequency Ranges: 150–167 MHz, 600–668 MHz, 1.2–1.33 GHz, or 2.4–2.67 GHz ! Jitter Generation as low as 0.5 psRMS for 622 MHz Output ! Accepts Input Clock from 9.4–668 MHz ! Regenerates a “Clean”, Jitter- Attenuated Version of Input Clock ! DSPLL™ Technology Provides Superior Jitter Performance ! Small Footprint: 4 mm x 4 mm ! Low Power: 310 mW typical ! SONET/SDH Systems ! Terabit Routers ! Digital Cross Connects ! Optical Transceiver Modules ! Gigabit Ethernet Systems ! Hybrid VCO Modules D SPL L TM P hase -Locke d Loop BU F BU F CL KIN+ CL KIN– 2 M U L TSEL 1 –0 RE F C L K + RE F C L K – 2 2 2 LO L MU L TO U T + M U LTO U T– CL KO UT+ CL KO UT– Bia s G en RE X T BU F Ca libra tion R e ge ne ratio n P W RDN/CAL 2 Ordering Information: See page 22. Pin Assignments Si5311 1 2 3 4 5 6 7 8 9 13 14 15 16 REXT VDD GND REFCLK+ REFCLK– PWRDN/CAL VDD CLKOUT+ CLKOUT– VDD 12 11 10 GND 17 18 19 20 Pad Top View PRELIMINARY DATA SHEET |
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