MT3170B/71B, MT3270B/71B, MT3370B/71B

Data Sheet

4

Zarlink Semiconductor Inc.

AGC is activated to prevent the input signal from being clipped. At low input level, the AGC remains inactive and the

input signal is passed directly to the hardware DTMF detection algorithm and to the energy detection circuit.

Filter and Decoder Section

The signal entering the DTMF detection circuitry is filtered by a notch filter at 350 and 440 Hz for dial tone rejection.

order switched capacitor bandpass filters. The high group and low group tones are then smoothed by separate

output filters and squared by high gain limiting comparators. The resulting squarewave signals are applied to a

digital detection circuit where an averaging algorithm is employed to determine the valid DTMF signal. For

MT3x70B, upon recognition of a valid frequency from each tone group, the early steering (ESt) output will go high,

indicating that a DTMF tone has been detected. Any subsequent loss of DTMF signal condition will cause the ESt

pin to go low. For MT3x71B, an internal delayed steering counter validates the early steering signal after a

predetermined guard time which requires no external components. The delayed steering (DStD) will go high only

when the validation period has elapsed. Once the DStD output is high, the subsequent loss of early steering signal

due to DTMF signal dropout will activate the internal counter for a validation of tone absent guard time. The DStD

output will go low only after this validation period.

Energy Detection

The output signal from the AGC circuit is also applied to the energy detection circuit. The detection circuit consists

of a threshold comparator and an active integrator. When the signal level is above the threshold of the internal

comparator (-35dBm), the energy detector produces an energy present indication on the SD output. The integrator

ensures the SD output will remain at high even though the input signal is changing. When the input signal is

removed, the SD output will go low following the integrator decay time. Short decay time enables the signal

envelope (or cadence) to be generated at the SD output. An external microcontroller can monitor this output for

specific call progress signals. Since presence of speech and DTMF signals (above the threshold limit) can cause

the SD output to toggle, both ESt (DStD) and SD outputs should be monitored to ensure correct signal identification.

As the energy detector is multiplexed with the digital serial data output at the SD pin, the detector output is selected

at all times except during the time between the rising edge of the first pulse and the falling edge of the fourth pulse

applied at the ACK pin.

Serial Data (SD) Output

When a valid DTMF signal burst is present, ESt or DStD will go high. The application of four clock pulses on the

ACK pin will provide a 4-bit serial binary code representing the decoded DTMF digit on the SD pin output. The rising

edge of the first pulse applied on the ACK pin latches and shifts the least significant bit of the decoded digit on the

SD pin. The next three pulses on ACK pin will shift the remaining latched bits in a serial format (see Figure 5). If less

than four pulses are applied to the ACK pin, new data cannot be latched even though ESt/DStD can be valid. Clock

pulses should be applied to clock out any remaining data bits to resume normal operation. Any transitions in excess

of four pulses will be ignored until the next rising edge of the ESt/DStD. ACK should idle at logic low. The 4-bit

binary representing all 16 standard DTMF digits are shown in Table 1.

DIGIT

697

1209

1

0

0

0

1

697

1336

2

0

0

1

0

697

1477

3

0

0

1

1

770

1209

4

0

1

0

0

770

1336

5

0

1

0

1

770

1477

6

0

1

1

0

852

1209

7

0

1

1

1