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K7Q161862 Datasheet(PDF) 7 Page - Samsung semiconductor |
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K7Q161862 Datasheet(HTML) 7 Page - Samsung semiconductor |
7 / 17 page 512Kx36 & 1Mx18 QDRTM b2 SRAM - 7 - Rev 1.0 Mar. 2004 K7Q163662B K7Q161862B READ DDR READ DDR WRITE READ NOP POWER-UP WRITE NOP LOAD NEW WRITE ADDRESS LOAD NEW READ ADDRESS ALWAYS (FIXED) WRITE STATE DIAGRAM Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1. 2. "READ" refers to read active status with R=Low, "READ" refers to read inactive status with R=high. "WRITE" and "WRITE" are the same case. 3. Read and write state machine can be active simultaneously. 4. State machine control timing sequence is controlled by K. ALWAYS (FIXED) READ WRITE READ WRITE READ WRITE |
Similar Part No. - K7Q161862 |
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Similar Description - K7Q161862 |
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