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April 10, 2001

 2001 Integrated Device Technology, Inc.

DSC 9096

64-Bit RISC Microprocessor

Features

Features

Features

Features

x

True 64-bit microprocessor

– 64-bit integer operations

– 64-bit floating-point operations

– 64-bit registers

– 64-bit virtual address space

x

High-performance microprocessor

– 260 Dhrystone MIPS at 200MHz

– 100 peak MFLOP/s at 200MHz

– Two-way set associative caches

– Simple 5-stage pipeline

x

High level of integration

– 64-bit, 200 MHz integer CPU

– 64-bit floating-point unit

– 16KB instruction cache

– 16KB data cache

– Flexible MMU with large, fully associative TLB

x

Low-power operation

– 3.3V power supply, for the “RV” part

– 5V power supply, for the “R” part

– Dynamic power management

– Standby mode reduces internal power

x

x

Available in 179-pin PGA or 208-pin QFP

x

Available at 80-200MHz, with mode bit dependent output

clock frequencies

x

64GB physical address space

x

Processor family for a wide variety of embedded

applications

– LAN switches

– Routers

– Color printers

Description

Description

Description

Description

The IDT79R4700 64-bit RISC Microprocessor is both software and

capabilities, the R4700 provides more computational power and data

movement bandwidth than is delivered to typical embedded systems by

32-bit processors.

development of R4700-based systems, allowing a variety of customers

access to the MIPS Open Architecture philosophy.

Block Diagram

Block Diagram

Block Diagram

Block Diagram

The IDT logo is a registered trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trade-

marks of Integrated Device Technology, Inc.

Read Buffer

Integer Register File

Integer/Address Adder

Data TLB Virtual

Shifter/Store Aligner

Logic Unit

Program Counter

PC Increm enter

Branch Adder

Load Aligner

Floating-point

Unpacker/Packer

Floating-point

Add/Sub/Cvt/Div/Sqrt

Integer Divide

Floating-point/Integer

Phase Lock Loop, Clocks

Instruction TLB Virtual

Joint TLB

Data Set A

Data Set B

Data Tag A

DTLB Physical

Address Buffer

Data Tag B

Instruction Tag A

Instruction Tag B

ITLB Physical

Store Buffer

Write Buffer

DVA

IVA

Instruction Set A

Instruction Set B

Multiply

SysAD

IBus

DBus

Coprocessor 0

System /Mem ory

Control

Tag

AuxTag

Instruction Select

Control

Instruction Register

Register File

IDT79R4700