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IDT72T40118L4BBI Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT72T40118L4BBI Datasheet(HTML) 3 Page - Integrated Device Technology |
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3 / 52 page  3 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 DESCRIPTION The IDT72T4088/72T4098/72T40108/72T40118 are exceptionally deep, extremelyhighspeed,CMOSFirst-In-First-Out(FIFO)memorieswiththeability to read and write data on both rising and falling edges of clock. The device has a flexible x40/x20/x10 Bus-Matching mode and the option to select single or doubledataratesforinputandoutputports.TheseFIFOsofferseveralkeyuser benefits: • Flexible x40/x20/x10 Bus-Matching on both read and write ports • Ability to read and write on both rising and falling edges of a clock • User selectable Single or Double Data Rate of input and output ports • A user selectable MARK location for retransmit • User selectable I/O structure for HSTL or LVTTL • Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittento an empty FIFO to the time it can be read, is fixed and short. • High density offerings up to 5Mbit • High speed operation of up to 250MHz Bus-Matching Double Data Rate FIFOs are particularly appropriate for network,video,telecommunications,datacommunicationsandotherapplica- tions that require fast data transfer on both rising and falling edges of the clock. This is a great alternative to increasing data rate without extending the width of the bus or the speed of the device. They are also effective in applications that need to buffer large amounts of data and match buses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either a 40-bit, 20-bit, or a 10-bit width as determined by the state of external control pins Input Width (IW), Output Width (OW), and Bus- Matching (BM) pin during the Master Reset cycle. TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable ( WEN) input. Data present on the Dn data inputs can be written into the FIFO on every rising and falling edge of WCLK when WEN is asserted and Write Single Data Rate ( WSDR) pin held HIGH. Data can be selected to write only on the rising edges of WCLK if WSDRisasserted.Toguaranteefunctionality of the device, WEN must be a controlled signal and not tied to ground. This is importantbecause WENmustbeHIGHduringthetimewhentheMasterReset ( MRS) pulse is LOW. In addition, the WSDR pin must be tied HIGH or LOW. It is not a controlled signal and cannot be changed during FIFO operation. WriteoperationscanbeselectedforeitherSingleorDoubleDataRatemode. For Single Data Rate operation, writing into the FIFO requires the Write Single Data Rate ( WSDR)pintobeasserted.DatawillbewrittenintotheFIFOonthe rising edge of WCLK when the Write Enable ( WEN) is asserted. For Double Data Rate operations, writing into the FIFO requires WSDRtobedeasserted. Data will be written into the FIFO on both rising and falling edge of WCLK when WENisasserted. The output port is controlled by a Read Clock (RCLK) input and a Read Enable( REN)input.DataisreadfromtheFIFOoneveryrisingandfallingedge of RCLK when REN is asserted and Read Single Data Rate (RSDR) pin held HIGH. Data can be selected to read only on the rising edges of RCLK if RSDR is asserted. To guarantee functionality of the device, RENmustbeacontrolled signal and not tied to ground. This is important because REN must be HIGH during the time when the Master Reset ( MRS) pulse is LOW. In addition, the RSDR pin must be tied HIGH or LOW. It is not a controlled signal and cannot be changed during FIFO operation. ReadoperationscanbeselectedforeitherSingleorDoubleDataRatemode. Similartothewriteoperations,readingfromtheFIFOinsingledataraterequires the Read Single Data Rate ( RSDR) pin to be asserted. Data will be read from the FIFO on the rising edge of RCLK when the Read Enable ( REN)isasserted. For Double Data Rate operations, reading into the FIFO requires RSDRtobe deasserted. Data will be read out of the FIFO on both rising and falling edge of RCLK when and REN is asserted. Boththeinputandoutput portcanbeselectedforeither2.5V LVTTLorHSTL operation. This can be achieved by tying the HSTL signal LOW for LVTTL or HIGHforHSTLvoltageoperation. WhenthereadportissetupforHSTLmode, theReadChipSelect( RCS)inputalsohasthebenefitofdisablingthereadport inputs, providing additional power savings. Thereistheoptionofselectingdifferentdataratesontheinputandoutputports ofthedevice.Thereareatotaloffourcombinationstochoosefrom,DoubleData Rate to Double Data Rate (DDR to DDR), DDR to Single Data Rate (DDR to SDR),SDRtoDDR,andSDRtoSDR.Theratescanbesetupusingthe WSDR and RSDRpins.Forexample,tosetuptheinputtooutputcombinationofDDR toSDR, WSDRwillbeHIGHandRSDRwillbeLOW.Readandwriteoperations are initiated on the rising edge of RCLK and WCLK respectively, never on the falling edge. If REN or WENisassertedafterarisingedgeofclock,noreador write operations will be possible on the falling edge of that same pulse. An Output Enable ( OE) input is provided for high-impedance control of the outputs. A read Chip Select ( RCS) input is also provided for synchronous enable/disable of the read port control input, REN. TheRCSinputissynchro- nized to the read clock, and also provides high-impedance controls to the Qn data outputs. When RCS is disabled, REN will be disabled internally and the data outputs will be in High-Impedance. Unlike the Read Chip Select signal however, OE is not synchronous to RCLK. Outputs are high-impedanced shortly after a delay time when the OE transitions from LOW to HIGH. The Echo Read Enable ( EREN) and Echo Read Clock (ERCLK) outputs areusedtoprovidetightersynchronizationbetweenthedatabeingtransmitted from the Qn outputs and the data being received by the input device. These output signals from the read port are required for high-speed data communi- cations.Datareadfromthereadportisavailableontheoutputbuswithrespect to EREN and ERCLK, which is useful when data is being read at high-speed operations where synchronization is important. ThefrequenciesofboththeRCLKandWCLKsignalsmayvaryfrom0tofMAX withcompleteindependence.Therearenorestrictionsonthefrequencyofone clock input with respect to another. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. InIDTStandardmode, thefirstwordwrittentoanemptyFIFOwillnotappear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating RENandenablingarisingRCLKedge, will shift the word from internal memory to the data output lines. Be aware that in Double Data Rate (DDR) mode only the IDT Standard mode is available. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of RCLK. A read operation does not have to be performed to access the first word written to the FIFO. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT input during Master Reset determines the timing mode in use. ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFOcan provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. These FIFOs have four flag pins, EF/OR(EmptyFlagorOutputReady),FF/ IR (Full Flag or Input Ready), PAE (Programmable Almost-Empty flag), and PAF(ProgrammableAlmost-Fullflag).TheEFandFFfunctionsareselected in IDT Standard mode. The IRandORfunctionsareselectedinFWFTmode. PAE and PAF are always available for use, irrespective of timing mode. |
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