IN74HC74AD datasheet(4/5 Pages) INTEGRAL

Part #	IN74HC74AD

Description	Dual D Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS

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Manufacturer	INTEGRAL [Integral Corp.]

Direct Link	http://www.iksemi.com/

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IN74HC74A

82

AC ELECTRICAL CHARACTERISTICS(C

L=50pF,Input tr=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

V

25

°C

to

-55

°C

≤85°C

≤125°C

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

2.0

4.5

6.0

30

35

4.8

24

28

4.0

20

24

MHz

tPLH, tPHL

Maximum Propagation Delay, Clock to Q or Q

(Figures 1 and 4)

2.0

4.5

6.0

100

20

17

125

25

21

150

30

26

ns

tPLH, tPHL

Maximum Propagation Delay, Set or Reset to Q

or Q (Figures 2 and 4)

2.0

4.5

6.0

105

21

18

130

26

22

160

32

27

ns

tTLH, tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

2.0

4.5

6.0

75

15

13

95

19

16

110

22

19

ns

CIN

Maximum Input Capacitance

-

10

pF

Power Dissipation Capacitance (Per Flip-Flop)

Typical @25

°C,V

CC=5.0 V

CPD

Used to determine the no-load dynamic power

consumption:

PD=CPDVCC

2f+I

CCVCC

39

pF

TIMING REQUIREMENTS(C

L=50pF,Input tr=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

V

25

°C to-55°C

≤85°C

≤125°C

Unit

tsu

Minimum Setup Time, Data to Clock

(Figure 3)

2.0

4.5

6.0

80

16

14

100

20

17

120

24

20

ns

th

Minimum Hold Time, Clock to Data

(Figure 3)

2.0

4.5

6.0

3.0

ns

trec

Minimum Recovery Time, Set or

Reset Inactive to Clock (Figure 2)

2.0

4.5

6.0

8.0

ns

tw

Minimum Pulse Width, Clock (Figure

1)

2.0

4.5

6.0

60

12

10

75

15

13

90

18

15

ns

tw

Minimum Pulse Width, Set or Reset

(Figure 2)

2.0

4.5

6.0

60

12

10

75

15

13

90

18

15

ns

tr, tf

Maximum Input Rise and Fall Times

(Figure 1)

2.0

4.5

6.0

1000

500

400

1000

500

400

1000

500

400

ns

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IN74HC74AD Datasheet(PDF) 4 Page - Integral Corp.

IN74HC74AD Datasheet(HTML) 4 Page - Integral Corp.

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