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IDT7202 Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT7202 Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 14 page 6 COMMERCIAL,INDUSTRIALANDMILITARY TEMPERATURERANGES IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1,024 x 9 Device Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by grounding the Expansion In ( XI). The IDT7200/7201A/7202A can be made to retransmit data when the RetransmitEnablecontrol( RT)inputispulsedLOW. Aretransmitoperationwill settheinternalreadpointertothefirstlocationandwillnotaffectthewritepointer. Read Enable ( R) and Write Enable (W) must be in the HIGH state during retransmit. This feature is useful when less than 256/512/1,024 writes are performed between resets. The retransmit feature is not compatible with the Depth Expansion Mode and will affect the Half-Full Flag ( HF), depending on the relative locations of the read and write pointers. EXPANSION IN ( XI) This input is a dual-purpose pin. Expansion In ( XI)isgroundedtoindicate an operation in the single device mode. Expansion In ( XI) is connected to Expansion Out ( XO) of the previous device in the Depth Expansion or Daisy Chain Mode. OUTPUTS: FULL FLAG ( FF) The Full Flag ( FF)willgoLOW,inhibitingfurtherwriteoperation,whenthe write pointer is one location less than the read pointer, indicating that the device is full. If the read pointer is not moved after Reset ( RS), the Full-Flag ( FF)willgoLOWafter256writesforIDT7200,512writesfortheIDT7201Aand 1,024 writes for the IDT7202A. EMPTY FLAG ( EF) The Empty Flag ( EF)willgoLOW,inhibitingfurtherreadoperations,when the read pointer is equal to the write pointer, indicating that the device is empty. EXPANSION OUT/HALF-FULL FLAG ( XO/HF) This is a dual-purpose output. In the single device mode, when Expansion In ( XI) is grounded, this output acts as an indication of a half-full memory. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag ( HF) will be set LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag ( HF) is then reset by using rising edge of the read operation. IntheDepthExpansionMode,ExpansionIn( XI)isconnectedtoExpansion Out ( XO)ofthepreviousdevice.Thisoutputactsasasignaltothenextdevice in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last location of memory. DATA OUTPUTS (Q0 – Q8) Data outputs for 9-bit wide data. This data is in a high impedance condition whenever Read ( R) is in a HIGH state. SIGNAL DESCRIPTIONS INPUTS: DATA IN (D0 – D8) Data inputs for 9-bit wide data. CONTROLS: RESET ( RS) Reset is accomplished whenever the Reset ( RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power up before a write operation can take place. Both the Read Enable ( R) and Write Enable (W) inputs must be in the HIGH state during the window shown in Figure 2, (i.e., tRSS before the rising edge of RS) and should not change until tRSR after the rising edge of RS. Half-Full Flag (HF) will be reset to HIGH after Reset ( RS). WRITE ENABLE ( W) A write cycle is initiated on the falling edge of this input if the Full Flag ( FF) isnotset. Dataset-upandholdtimesmustbeadheredtowithrespecttotherising edge of the Write Enable ( W). DataisstoredintheRAMarraysequentiallyand independently of any on-going read operation. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag ( HF)willbesettoLOWandwillremainsetuntilthe difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag ( HF)isthenreset by the rising edge of the read operation. To prevent data overflow, the Full Flag ( FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read operation, the Full Flag( FF)willgoHIGHaftertRFF,allowingavalidwritetobegin. WhentheFIFO is full, the internal write pointer is blocked from W,soexternalchangesinWwill not affect the FIFO when it is full. READ ENABLE ( R) A read cycle is initiated on the falling edge of the Read Enable ( R)provided theEmptyFlag( EF)isnotset. ThedataisaccessedonaFirst-In/First-Outbasis, independent of any ongoing write operations. After Read Enable ( R) goes HIGH,theDataOutputs(Q0– Q8)willreturntoahighimpedanceconditionuntil thenextReadoperation. WhenalldatahasbeenreadfromtheFIFO,theEmpty Flag ( EF)willgoLOW,allowingthe“final”readcyclebutinhibitingfurtherread operations with the data outputs remaining in a high impedance state. Once a validwriteoperationhasbeenaccomplished,theEmptyFlag( EF)willgoHIGH aftertWEFandavalidReadcanthenbegin. WhentheFIFOisempty,theinternal read pointer is blocked from RsoexternalchangesinRwillnotaffecttheFIFO when it is empty. FIRST LOAD/RETRANSMIT ( FL/RT) This is a dual-purpose input. In the Depth Expansion Mode, this pin is groundedtoindicatethatitisthefirstloaded(seeOperatingModes). IntheSingle |
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