Electronic Components Datasheet Search |
|
ICM107 Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers |
|
ICM107 Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers |
4 / 20 page ICM107B Mega pixel CMOS sensor Data Sheet Version 1.0 July 2002 ©2000, 2001,2002 IC Media Corporation & IC Media Technology Corp 10/29/2002 web site: http://www.ic-media.com/ web site: http://www.ic-media.com.tw/ page 4 Confidential 1. Preliminary Pin Assignment Pin # Name Class* Function 14 CLKSEL D, I, N Clock source selection 0: clocks pass PLL, use XIN (pin 12) 1: bypass PLL, use CLKIN (pin 11) 11 CLKIN D, I, N External clock source; bypass PLL 12 XIN A, I Crystal oscillator in, or external clock in; if external clocks used, leave Xout (pin 13) unconnected 13 XOUT A, O Crystal oscillator out 33 PCLK D, O Pixel clock output 35 OEN D, I, N Output enable. 0: enable, 1: disable 31 SIF ID D, I, N LSB of SIF slave address 32 MSSEL D, I, U SIF master/slave selection. 0: slave, 1: master 2 SCL D, I/O SIF clock 1 SDA D, I/O SIF data 10 POWERDN D, I, N Power down control, 0: power down, 1: active 17 RSET A, I Resistor to ground = 25 K Ω @ 48 MHz main clock, (or 50K Ω @ 24 MHz main clock) 8 RSTN D, I, U Chip reset, active low 48 DOUT[10] D, I/O Data output bit 10 47 DOUT[9] D, I/O Data output bit 9 46 DOUT[8] D, I/O Data output bit 8 45 DOUT[7] D, O Data output bit 7 44 DOUT[6] D, I/O Data output bit 6; if pulled up/down, the initial value of TIMING_CONTROL_LOW[2] (VSYNC polarity) is 1/0 43 DOUT[5] D, I/O Data output bit 5; if pulled up/down, the initial value of TIMING_CONTROL_LOW[1] (HSYNC polarity) is 1/0 40 DOUT[4] D, I/O Data output bit 4; if pulled up/down, the initial value of AD_IDL[3] (Sub ID) is 1/0 39 DOUT[3] D, I/O Data output bit 3; if pulled up/down, the initial value of AD_IDL[2] (Sub ID) is 1/0 38 DOUT[2] D, I/O Data output bit 2; if pulled up/down, the initial value of AD_IDL[1] (Sub ID) is 1/0 37 DOUT[1] D, I/O Data output bit 1; if pulled up/down, the initial value of AD_IDL[0] (Sub ID) is 1/0 36 DOUT[0] D, I/O Data output bit 0; if pulled up/down, the synchronization mode is in master/slave mode which requires HSYNC and VSYNC operating in output/input mode 3 HSYNC D, I/O Horizontal sync signal 5 VSYNC D, I/O Vertical sync signal 34 FLASH D, O Flash light control 15 RAMP A, O Analog ramp output 30,7 VDDA P Sensor analog power 29,9 GNDA P Sensor analog ground 19 VDDD P Sensor digital power 18 GNDD P Sensor digital ground 41,4 VDDK P Digital power |
Similar Part No. - ICM107 |
|
Similar Description - ICM107 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |