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CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *K
Page 5 of 53
INA1+
INA1
INA2+
INA2
INSELA
TXLBA
INB1+
INB1
INB2+
INB2
INSELB
TXLBB
INC1+
INC1
INC2+
INC2
INSELC
TXLBC
IND1+
IND1
IND2+
IND2
INSELD
TXLBD
Character-Rate Clock
Clock &
Data
Recovery
PLL
Clock &
Data
Recovery
PLL
Clock &
Data
Recovery
PLL
Clock &
Data
Recovery
PLL
LPEN
LFID
LFIC
LFIB
LFIA
8
RXSTC[2:0]
RXDC[7:0]
RXOPC
3
8
RXSTB[2:0]
RXDB[7:0]
RXOPB
3
8
RXSTD[2:0]
RXDD[7:0]
RXOPD
3
8
RXSTA[2:0]
RXDA[7:0]
RXOPA
3
Receive
Signal
Monitor
Receive
Signal
Monitor
Receive
Signal
Monitor
Receive
Signal
Monitor
RXCLKD+
RXCLKD
Parity Control
2
RXCLKC+
RXCLKC
2
RXCLKB+
RXCLKB
2
RXCLKA+
RXCLKA
2
RXRATE
FRAMCHAR
RFMODE
RFEN
RXMODE[1:0]
SDASEL
JTAG
Boundary
Scan
Controller
TDO
TMS
TCLK
TDI
Clock
Select
Clock
Select
Clock
Select
Clock
Select
Bonding
Control
BOND_ALL
BONDST
BOND_INH
RXCKSEL
TRSTZ
2
2
DECMODE
MASTER
Receive Path Block Diagram
= Internal Signal
RBIST[D:A]
RX PLL Enable
Latch
RXLE
BOE[7:0]
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