CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *K
Page 11 of 53
RXCLKA
RXCLKB
RXCLKC
RXCLKD
Three-state, LVTTL
Output clock or static
control input
Receive Character Clock Output or Clock Select Input. When configured such that
all output data paths are clocked by the recovered clock (RXCKSEL = MID), these
true and complement clocks are the receive interface clocks which are used to control
timing of output data (RXDx[7:0], RXSTx[2:0] and RXOPx). These clocks are output
continuously at either the dual-character rate (1/20th the serial bit-rate) or character
rate (1/10th the serial bit-rate) of the data being received, as selected by RXRATE.
When configured such that all output data paths are clocked by REFCLK instead of a
recovered clock (RXCKSEL = LOW), the RXCLKA and RXCLKC output drivers
present a buffered and delayed form of REFCLK. RXCLKA and RXCLKC are
buffered forms of REFCLK that are slightly different in phase. This phase difference
allows the user to select the optimal setup/hold timing for their specific interface.
When RXCKSEL = LOW and quad channel bonding is enabled, RXCLKB+ and
RXCLKD+ are static control inputs used to select the master channel for bonding and
status control.
When RXCKSEL = HIGH and quad-channel bonding is enabled, one of the recovered
clocks from channels A, B, C or D can be selected to clock the bonded output data.
The selection of the recovered clock is made by RXCLKB+ and RXCLKD+ which act
as static control inputs in this mode. Both RXCLKA and RXCLKC output buffered
forms of the recovered clock selected from receive channel A, B, C, or D. See Table 15
for details.
When RXCKSEL = HIGH and dual-channel bonding is enabled, one of the recovered
clocks from channels A or B is selected to present bonded data from channels A and
B, and one of the recovered clocks from channels C or D is selected to present bonded
data from channels C and D. RXCLKA output the recovered clock from either receive
channel A or receive channel B as selected by RXCLKB+ to clock the bonded output
data from channels A and B, and RXCLKC output the recovered clock from either
receive channel C or receive channel D as selected by RXCLKD+ to the clock the
bonded output data from channels C and D. See Table 16 for details.
RXCKSEL
Three-level Select [5],
static control input
Receive Clock Mode. Selects the receive clock source used to transfer data to the
Output Registers.
When LOW, all four Output Registers are clocked by REFCLK. RXCLKB and
RXCLKD outputs are disabled (High-Z), and RXCLKA and RXCLKC present
buffered and delayed forms of REFCLK. This clocking mode is required for channel
bonding across multiple devices.
When MID, each RXCLKx output follows the recovered clock for the respective
channel, as selected by RXRATE. When the 10B/8B Decoder and Elasticity Buffer are
bypassed (DECMODE = LOW), RXCKSEL must be MID.
When HIGH and channel bonding is enabled in dual-channel mode (RX modes 3 and
5), RXCLKA outputs the recovered clock from either receive channel A or B as
selected by RXCLKB+, and RXCLKC outputs the recovered clock from either receive
channel C or D as selected by RXCLKD+. These output clocks may operate at the
character-rate or half the character-rate as selected by RXRATE.
When HIGH and channel bonding is enabled in quad channel mode (RX modes 6 and
8), or if the receive channels are operated in independent mode (RX modes 0 and 2),
RXCLKA and RXCLKC output the recovered clock from receive channel A, B, C,
or D, as selected by RXCLKB+ and RXCLKD+. This output clock may operate at the
character-rate or half the character-rate as selected by RXRATE.
Pin Descriptions (continued)
CYP(V)15G0401DXB Quad HOTLink II Transceiver
Pin Name
I/O Characteristics
Signal Description
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
