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COP87L22CJM-2N Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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COP87L22CJM-2N Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 32 page COP820CJ Pin Assignment Port Typ ALT 16 20 28 Pin Funct Pin Pin Pin L0 IO MIWUCMPOUT 5 7 11 L1 IO MIWUCMPINb 68 12 L2 IO MIWUCMPINa 79 13 L3 IO MIWU 8 10 14 L4 IO MIWU 9 11 15 L5 IO MIWU 10 12 16 L6 IO MIWU 11 13 17 L7 IO MIWUMODOUT 12 14 18 G0 IO INTR 17 25 G1 IO 18 26 G2 IO 19 27 G3 IO TIO 15 20 28 G4 IO SO 1 1 G5 IO SK 16 2 2 G6 I SI 133 G7 I CKO 2 4 4 I0 I 7 I1 I 8 I2 I 9 I3 I 10 D0 O 19 D1 O 20 D2 O 21 D3 O 22 VCC 466 GND 13 15 23 CKI 3 5 5 RESET 14 16 24 Pin Description VCC and GND are the power supply pins CKI is the clock input This can come from an external source a RC generated oscillator or a crystal (in conjunc- tion with CKO) See Oscillator description RESET is the master reset input See Reset description PORT I is a 4-bit Hi-Z input port PORT L is an 8-bit IO port There are two registers associated with the L port a data register and a configuration register Therefore each L IO bit can be individually configured under software control as shown below Port L Port L Port L Config Data Setup 0 0 Hi-Z Input (TRI-STATE) 0 1 Input with Weak Pull-up 1 0 Push-pull Zero Output 1 1 Push-pull One Output Three data memory address locations are allocated for this port one each for data register 00D0 configuration regis- ter 00D1 and the input pins 00D2 Port L has the following alternate features L0 MIWU or CMPOUT L1 MIWU or CMPINb L2 MIWU or CMPINa L3 MIWU L4 MIWU (high sink current capability) L5 MIWU (high sink current capability) L6 MIWU (high sink current capability) L7 MIWU or MODOUT (high sink current capability) The selection of alternate Port L functions is done through registers WKEN 00C9 to enable MIWU and CNTRL2 00CC to enable comparator and modulator All eight L-pins have Schmitt Triggers on their inputs PORT G is an 8-bit port with 6 IO pins (G0 – G5) and 2 input pins (G6 G7) All eight G-pins have Schmitt Triggers on the inputs There are two registers associated with the G port a data register and a configuration register Therefore each G port bit can be individually configured under software control as shown below Port G Port G Port G Config Data Setup 0 0 Hi-Z Input (TRI-STATE) 0 1 Input with Weak Pull-up 1 0 Push-pull Zero Output 1 1 Push-pull One Output Three data memory address locations are allocated for this port one for data register 00D3 one for configuration reg- ister 00D5 and one for the input pins 00D6 Since G6 and G7 are Hi-Z input only pins any attempt by the user to configure them as outputs by writing a one to the configura- tion register will be disregarded Reading the G6 and G7 configuration bits will return zeros Note that the device will be placed in the Halt mode by writing a ‘‘1’’ to the G7 data bit Six pins of Port G have alternate features G0 INTR (an external interrupt) G3 TIO (timercounter inputoutput) G4 SO (MICROWIRE serial data output) G5 SK (MICROWIRE clock IO) G6 SI (MICROWIRE serial data input) G7 CKO crystal oscillator output (selected by mask option) or HALT restart inputgeneral purpose input (if clock option is RC or external clock) http www nationalcom 6 |
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