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CAT93HC46STE13 Datasheet(PDF) 6 Page - Catalyst Semiconductor |
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CAT93HC46STE13 Datasheet(HTML) 6 Page - Catalyst Semiconductor |
6 / 9 page 6 CAT93HC46 Doc. No. 1008, Rev. G Erase/Write Enable and Disable The CAT93HC46 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once write is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93HC46 write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. Erase All Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self-timed clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self-timed mode. (Note 1.) The ready/busy status of the CAT93HC46 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory locations will return to a logical “1” state. Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self-timed data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self-timed mode. The ready/busy status of the CAT93HC46 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. Once written, the contents of all memory locations will return to a logical “0” state. Note 1: After the last data bit has been sampled, Chip Select (CS) must be brought Low before the next rising edge of the clock (SK) in order to start the self-timed high voltage cycle. This is important because if the CS is brought low before or after this specific frame window, the addressed location will not be programmed or erased. Figure 4. Erase Instruction Timing SK CS DI DO STANDBY HIGH-Z HIGH-Z 1 AN AN-1 BUSY READY STATUS VERIFY tSV tHZ tEW tCS MIN 11 A0 Figure 3. Write Instruction Timing SK CS DI DO tCS MIN STANDBY HIGH-Z HIGH-Z 101 AN AN-1 A0 DN D0 BUSY READY STATUS VERIFY tSV tHZ tEW |
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