5962-9459901MYC datasheet(9/10 Pages) ETC

Part #	5962-9459901MYC

Description	CMOS NV SRAM 8K X 8 AUTOSTORE NONVOLATILE STATIC RAM

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STK12C68-M

4-61

access cycle time is longer than 55ns.

Figure 2 below

shows the relationship between I

CC and access times

for READ cycles. All remaining inputs are assumed to

cycle, and current consumption is given for all inputs at

CMOS

or TTL levels.

Figure 3 shows the same relation-

ship for WRITE cycles.

When E is HIGH, the chip

consumes only standby currents, and these plots do

not apply.

The cycle time used in

Figure 2 corresponds to the

length of time from the later of the last address transi-

tion or E going LOW to the earlier of E going HIGH or the

next address transition. W is assumed to be HIGH,

while the state of G does not matter. Additional current

is consumed when the address lines change state

while E is asserted. The cycle time used in

Figure 3

corresponds to the length of time from the later of W or

E going LOW to the earlier of W or E going HIGH.

The overall average current drawn by the part depends

on the following items: 1) CMOS or TTL input levels; 2)

the time during which the chip is disabled (E HIGH); 3)

the cycle time for accesses (E LOW); 4) the ratio of

reads to writes; 5) the operating temperature; 6) the

V

CC level; and 7) output load.

WRITE

operation has taken place since the most recent

STORE

cycle. Note that if HSB is driven low via external

circuitry and no WRITEs have taken place, the part will

still be disabled until HSB is allowed to return HIGH.

Software initiated STORE cycles are performed regard-

less of whether or not a WRITE operation has taken

place.

PREVENTING AUTOMATIC STORES

The

AutoStore™ function can be disabled on the fly by

holding HSB HIGH with a driver capable of sourcing

15mA at a VOH of at least 2.2V as it will have to

overpower the internal pull-down device that drives

HSB low for 50ns at the onset of an

AutoStore™.

When

the

STK12C68-M

is

connected

for

AutoStore™operation (system V

CC connected to VCCX

and a 100uF capacitor on V

CAP) and VCC crosses

V

SWITCH on the way down, the STK12C68 will attempt

to pull HSB LOW ; if HSB doesn't actually get below V

IL,

the part will stop trying to pull HSB LOW and abort the

AutoStore™attempt.

LOW AVERAGE ACTIVE POWER

The STK12C68-M has been designed to draw signifi-

cantly less power when E is LOW (chip enabled) but the

100

80

60

40

20

50

100

150

200

0

TTL

CMOS

Cycle Time (ns)

100

80

60

40

20

50

100

150

200

0

TTL

CMOS

Cycle Time (ns)

1

28

26

V

HSB

CAP

CCX

VSS

14

0.1uF

Bypass

100uF

± 20%

+

Power

Supply

10K Ohms

(optional)

nvSRAM

Note: Typical at 25

° C

Figure 1

Schematic Diagram

Figure 2

ICC (Max) Reads

Figure 3

ICC (Max) Writes

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