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Z8S18006PEC Datasheet(PDF) 1 Page - Zilog, Inc.

Part # Z8S18006PEC
Description  ENHANCED Z180 MICROPROCESSOR
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z8S18006PEC Datasheet(HTML) 1 Page - Zilog, Inc.

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DS971800401
P R E L I M I N A R Y
1-1
1
PRELIMINARY PRODUCT SPECIFICATION
Z80180/Z8S180/
1
Z8L180 SL1919
ENHANCED Z180 MICROPROCESSOR
FEATURES
s
Code Compatible with Zilog Z80® CPU
s
Extended Instructions
s
Two Chain-Linked DMA Channels
s
Low Power-Down Modes
s
On-Chip Interrupt Controllers
s
Three On-Chip Wait-State Generators
s
On-Chip Oscillator/Generator
s
Expanded MMU Addressing (up to 1 MB)
s
Clocked Serial I/O Port
s
Two 16-Bit Counter/Timers
s
Two Enhanced UARTs (up to 512 Kbps)
s
Clock Speeds: 6, 8, 10, 20, 33 MHz
s
Operating Range: 5V (3.3V@ 20 MHz)
s
Operating Temperature Range: 0°C to +70°C
s
-40°C to +85°C Extended Temperature Range
s
Three Packaging Styles
68-Pin PLCC
64-Pin DIP
80-Pin QFP
GENERAL DESCRIPTION
The enhanced Z80180/Z8S180/Z8L180significantly im-
proves on the previous Z80180 models while still providing
full backward compatibility with existing Zilog Z80 devices.
The Z80180/Z8S180/Z8L180 now offers faster execution
speeds, power saving modes, and EMI noise reduction.
This enhanced Z180 design also incorporates additional
feature enhancements to the ASCIs, DMAs, and Icc
STANDBY Mode power consumption. With the addition of
“ESCC-like” Baud Rate Generators (BRGs), the two ASCIs
now have the flexibility and capability to transfer data asyn-
chronously at rates of up to 512 Kbps. In addition, the ASCI
receiver has added a 4-byte First In First Out (FIFO) which
can be used to buffer incoming data to reduce the inci-
dence of overrun errors. The DMAs have been modified to
allow for a “chain-linking” of the two DMA channels when
set to take their DMA requests from the same peripherals
device. This feature allows for non-stop DMA operation be-
tween the two DMA channels, reducing the amount of CPU
intervention (Figure 1).
Not only does the Z80180/Z8S180/Z8L180 consume less
power during normal operations than the previous model,
it has also been designed with three modes intended to fur-
ther reduce the power consumption. Zilog reduced Icc pow-
er consumption during STANDBY Mode to a minimum of
10
µA by stopping the external oscillators and internal
clock. The SLEEP mode reduces power by placing the
CPU into a “stopped” state, thereby consuming less cur-
rent while the on-chip I/O device is still operating. The
SYSTEM STOP mode places both the CPU and the on-
chip peripherals into a “stopped” mode, thereby reducing
power consumption even further.
A new clock doubler feature has been implemented in the
Z80180/Z8S180/Z8L180 device that allows the program-
mer to double the internal clock from that of the external
clock. This provides a systems cost savings by allowing
the use of lower cost, lower frequency crystals instead of
the higher cost, and higher speed oscillators.
The Enhanced Z180 is housed in 80-pin QFP, 68-pin
PLCC, and 64-pin DIP packages.


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