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PRELIMINARY

XRT95L51

OC-48 ATM UNI/POS/MAPPER IC

JULY 2000

REV. P1.0.1

GENERAL DESCRIPTION

The XRT95L51 is an ATM/PPP physical layer proces-

sor with integrated SONET OC-48/STM-16 framing

controller. ATM direct mapping and cell delineation

are supported, as are PPP mapping and frame pro-

cessing. The XRT95L51 contains an integral SONET

framer which provides framing and error accumula-

tion in accordance with ANSI/ITU-T specifications.

The configuration of this device is done through inter-

nal registers accessible via 8-bit parallel, memory

mapped, microprocessor interface.

The XRT95L51 provides full section, line and path

overhead processing and supports scrambling/de-

scrambling, alarm signal insertion/detection and bit

interleaved parity processing.

The SONET/SDH transmit and receive blocks are

used to transmit/receive an OC-48c/STM-16c signal

or compose and decompose four OC-12/12c sig-

nals.The blocks operate at a peak internal clock

speed of 77 MHz and support 32-bit internal data

paths. The transmit and receive blocks are compliant

with both SONET and SDH standards.

APPLICATIONS

• Digital Cross Connect Systems

• ATM Switches

• Routers

• SONET/SDH Add Drop Multiplexers

• Multiplexers

FEATURES

• Single chip for ATM UNI and Packet over SONET.

• Generates and terminates SONET section, line and

path layers.

• Provides SONET frame scrambling and descram-

bling.

• Provides 32-bit data UTOPIA level II and III multi-

PHY interface and POS-PHY interface.

• 8-bit microprocessor interface

• Includes ATM cell or PPP packet mapping

• Single +3.3V power supply with +5V input tolerance

• -40°C to +85°C Operating Temperature Range

• Available in a 388 pin PBGA package

Parallel to Serial

Tx XCVR I/F

Serial to Parallel

Rx XCVR I/F

&

Byte Align

Tx OC-12

Mapper X4

Rx OC-12

MapperX4

Overhead

Extraction Block

Tx ATM Cell

Processor

Tx POS Cell

Processor

Rx POS Cell

Processor

Rx ATM Cell

Processor

POH Extract & Interpret

Tx Cell

Buffer

Tx Control

Rx Control

Rx Cell

Buffer

JTAG Test Port

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7[/'$7$>48=3@#.20

7[/357<#.20

7[/)3#.20

7[/567B/#.20

7[/&ON2#.20

7[5()&ON

Tx Framer

SOH Processor

POH Processor

Scrambler

Rx Framer

SOH Processor

POH Processor

Descrambler

5[/&ON#.20

5[/'$7$>48=3@#.20

5[/357<#.20

5[/)3#.20

5[/&ON3#.20

5[5()&ON

/26

5[8&ON

5[8(1B/

5[862&

5[8&/$9

5[8$''5>7=3@

5[8'$7$>64=3@

5[8357<

5[3(23

5[3(55

5[3'9$/

7[8&ON

7[8(1%/

7[862&

7[8&/$9

7[8$''5>7=3@

7[8'$7$>64=3@

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7[3(23

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32

32

Microprocessor Interface

Overhead

Insertion Block

POH Generation

& Insertion