VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC7961

3.125Gb/s PECL Limiting Amplifier with LOS Detect

Page 4

G52360-0, Rev 2.0

02/09/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Package Pin Descriptions

Figure 1: Pin Diagram

Table 5: Pin Identifications

Pin Name

Pin No.

Description

CZ1

1

Offset Correction Loop Capacitor. Place capacitor between this pin and CZ2 to alter time constant

of offset correction loop. See Detailed Description section.

CZ2

2

Offset Correction Loop Capacitor. Place capacitor between this pin and CZ1 to alter time constant

of offset correction loop. See Detailed Description section.

GND

3

Supply Ground

IN+

4

Noninverted Input Signal

IN-

5

Inverted Input Signal

GND

6

Supply Ground

NC

7

This pin may be either connected to ground of left unconnected. This pin does not effet the

performance of the device.

TH

8

Loss of Signal (LOS) Threshold. Connect a resistor from this pin to ground to set the input signal

level at which LOS outputs will be asserted. See Application Information section.

LOS

9

Inverted Loss of Signal Output. LOS is HIGH for input signals above the threshold programmed by

TH. See Detailed Description section.

LOS

10

Noninverted Loss of Signal Output. LOS is LOW for input signals above the threshold

programmed by TH. See Detailed Description section.

VCC

11

Power Supply

OUT-

12

Inverted Data Output

OUT+

13

Noninverted Data Output

VCC

14

Power Supply

SQUELCH

15

Squelch Input. Squelch is disabled if this pin is unconnected or set LOW. When SQUELCH is

HIGH, OUT+ and OUT- are forced to static levels. See Detailed Description section.

NC

16

No Connection

1

2

3

4

5

6

7

8

CZ1

CZ2

GND

IN+

IN-

GND

NC

TH

NC

SQUELCH

VCC

OUT+

OUT-

VCC

LOS

LOS

16

15

14

13

12

11

10

9

VSC7961

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TSSOP-16 Package