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TPS6508700RSKR Datasheet(PDF) 10 Page - Texas Instruments |
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TPS6508700RSKR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 100 page 10 TPS6508700 SWCS134 – OCTOBER 2017 www.ti.com Submit Documentation Feedback Product Folder Links: TPS6508700 Specifications Copyright © 2017, Texas Instruments Incorporated Electrical Characteristics: Reference and Monitoring System (continued) over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C) (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IQ Quiescent current VIN = 13 V, IOUT = 0 A 20 µA COUT External output capacitance 2.2 4.7 10 µF 4.7 Electrical Characteristics: Buck Controllers over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BUCK1 VIN Power input voltage for external HSD FET 5.6 13 21 V VFBVOU T1 Internal reference regulation voltage TA = 25°C 0.392 0.4 0.408 V ILIM_LSD Low-side output valley current limit accuracy (programmed by external resistor RLIM) –15% 15% ILIMREF Source current out of ILIM1 pin TA = 25°C 45 50 55 µA VLIM Voltage at ILIM1 pin VLIM = RLIM × ILIMREF 0.2 2.25 V VTH_PG Power good deassertion threshold in percentage of target VFB VOUT rising 105.5% 108% 110.5% VOUT falling 89.5% 92% 94.5% RDSON_ DRVH Driver DRVH resistance Source, IDRVH = –50 mA 3 Ω Sink, IDRVH = 50 mA 2 Ω RDSON_ DRVL Driver DRVL resistance Source, IDRVL = –50 mA 3 Ω Sink, IDRVL = 50 mA 0.4 Ω CBOOT Bootstrap capacitance 100 nF RON_BO OT Bootstrap switch ON resistance 20 Ω BUCK2, BUCK6 VIN Power input voltage for external HSD FET 5.6 13 21 V VOUT DC output voltage VID range and options VID step size = 10 mV, BUCKx_VID[6:0] progresses from 0000001b to 1111111b 0.41 1.67 V VID step size = 25 mV, BUCKx_VID[6:0] progresses from 0000001b to 1111111b 1 3.575 V BUCK2 output voltage default Set by BUCK2_VID[6:0], 10-mV step size selected 0.8 V BUCK6 output voltage default Set by BUCK6_VID[6:0], 25-mV step size selected 3.3 V DC output voltage accuracy VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V IOUT = 100 mA to 7 A –2% 2% Total output voltage accuracy (DC plus ripple) in DCM IOUT = 10 mA, VOUT ≤ 1 V –30 40 mV SR(VOU T) Output DVS slew rate Step size = 10 mV 2.5 3.125 mV/µs Step size = 25 mV 5 6.25 ILIM_LSD Low-side output valley current limit accuracy (programmed by external resistor RLIM) –15% 15% ILIMREF Source current out of ILIM1 pin TA = 25°C 45 50 55 µA VLIM Voltage at ILIM1 pin VLIM = RLIM × ILIMREF 0.2 2.25 V ΔVOUT/ ΔVIN Line regulation VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V, IOUT = 7 A –0.5% 0.5% |
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