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TAS5760M Datasheet(PDF) 10 Page - Texas Instruments |
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TAS5760M Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 77 page  10 TAS5760M-Q1 SLOS988 – SEPTEMBER 2017 www.ti.com Product Folder Links: TAS5760M-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Speaker Amplifier in Mono Parallel Bridge Tied Load (PBTL) Mode (continued) input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (1) The continuous power output of any amplifier is determined by the thermal performance of the amplifier as well as limitations placed on it by the system around it, such as the PCB configuration and the ambient operating temperature. The performance characteristics listed in this section are achievable on the TAS5760M-Q1's EVM, which is representative of the poplular "2 Layers / 1oz Copper" PCB configuration in a size that is representative of the amount of area often provided to the amplifier section of popular consumer audio electronics. As can be seen in the instantaneous power portion of this table, more power can be delivered from the TAS5760M-Q1 if steps are taken to pull more heat out of the device. For instance, using a board with more layers or adding a small heatsink will result in an increase of continuous power, up to and including the instantaneous power level. This behavior can also been seen in the POUT vs. PVDD plots shown in the Typical Characteristics (Mono PBTL Mode): fSPK_AMP = 384 kHz section of this data sheet. PO(SPK) Maximum Instantaneous Output Power PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 2Ω, THD+N = 0.1%, 28.6 W PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 4Ω, THD+N = 0.1%, 15.9 PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, THD+N = 0.1% 8.4 PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 2Ω, THD+N = 0.1%, 43.2 PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 4Ω, THD+N = 0.1%, 25 PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, THD+N = 0.1% 13.3 PVDD = 19 V, SPK_GAIN[1:0] Pins = 01, RSPK = 2Ω, THD+N = 0.1%, 68.3 PVDD = 19 V, SPK_GAIN[1:0] Pins = 01, RSPK = 4Ω, THD+N = 0.1%, 40 PVDD = 19 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, THD+N = 0.1% 21.3 PVDD = 24 V, SPK_GAIN[1:0] Pins = 10, RSPK = 2Ω, THD+N = 0.1%, 114.7 PVDD = 24 V, SPK_GAIN[1:0] Pins = 10, RSPK = 4Ω, THD+N = 0.1%, 63.5 PVDD = 24 V, SPK_GAIN[1:0] Pins = 10, RSPK = 8Ω, THD+N = 0.1% 34.1 PO(SPK) Maximum Continuous Output Power(1) PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 2Ω, THD+N = 0.1%, 30 W PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 4Ω, THD+N = 0.1%, 15.9 PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, THD+N = 0.1% 8.4 PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 2Ω, THD+N = 0.1%, 28.5 PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 4Ω, THD+N = 0.1%, 25 PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, THD+N = 0.1% 13.3 PVDD = 19 V, SPK_GAIN[1:0] Pins = 01, RSPK = 2Ω, THD+N = 0.1%, 26.5 PVDD = 19 V, SPK_GAIN[1:0] Pins = 01, RSPK = 4Ω, THD+N = 0.1%, 40 PVDD = 19 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, THD+N = 0.1% 21.3 PVDD = 24 V, SPK_GAIN[1:0] Pins = 10, RSPK = 2Ω, THD+N = 0.1%, 24 PVDD = 24 V, SPK_GAIN[1:0] Pins = 10, RSPK = 4Ω, THD+N = 0.1%, 40 PVDD = 24 V, SPK_GAIN[1:0] Pins = 10, RSPK = 8Ω, THD+N = 0.1% 34.1 |
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