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QT60320 Datasheet(PDF) 5 Page - Quantum Research Group |
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QT60320 Datasheet(HTML) 5 Page - Quantum Research Group |
5 / 14 page 2 - CIRCUIT SPECIFICS A basic QT60320D circuit is shown in Figure 2-1. 2.1 SIGNAL PATH The QT60320D requires an external sampling capacitor, two Cz capacitors, an amplifier, some analog switches, and an R2R ladder DAC to operate. The Cs capacitor performs the charge integration function by collecting charge coupled though a selected key during the dV/dt of the rising edge of an 'X' scan line. The charge is sampled 'n' times during the course of a burst of switching cycles of length 'n'. As the burst progresses the charge on Cs increases in a staircase fashion (Figure 1-4). At the burst's end the voltage on Cs, which is on the order of a few tenths of a volt, is amplified by a gain circuit which includes an offset current from the R2R ladder DAC driven by the X drive lines. The offset current from the R2R ladder repositions the output of the amplifier chain to coincide as closely as possible with the center span of the 60320's ADC, which can convert voltages between 0 and 5 volts. Between bursts the Cs reset mosfet is activated to reset the Cs capacitor to ground. Gain is directly controlled by burst length 'n', amplifier gain Av, and the values of Cs, Cz1 and Cz2. Only 'n' can be adjusted on a key by key basis whereas Av and the capacitances can only be adjusted for all keys. The amplifier should typically have a total positive gain of 100 +/- 20%.. If there is a large amount of coupling between X and Y lines, and where burst length 'n' is set to a high number, charge accumulation on Cs may reach a point where the ladder DAC can no longer offset the signal back into the ADC's usable range. In this case the circuit will employ one or two of the Cz capacitors to 'knock back' or cancel the charge accumulated on Cs; each Cz will cancel charge in a discrete step as required. LQ 5 QT60320D R1.11/12.07.03 Figure 2-1 Basic QT60320D Circuit X1 X2 X3 X4 X5 X6 X7 X8 YS1 YS2 YS3 YS4 CC 1 CC 2 CS AIN G GGG VVV Vcc Rst Rx Tx I1 I2 I3 I4 O1 O2 O3 O4 O5 O6 O7 O8 XT1 XT2 L1 L2 4 9 10 33 34 35 36 11 12 13 14 23 24 25 26 8 7 15 16 618 39 V 51 7 2 7 38 40 41 42 43 44 1 2 3 19 20 21 22 32 31 30 37 28 29 DS18 11 8MHz CAL L ED STAT LED C6 (Cz1) 8 20pF C7 (Cz2) 8 20pF BSN20 R2R dac 1 00K + _ + _ R3 68K R5 10K R4 100K R6 10K C5 (Cs) 15nF Vcc TL C22 72 UART I N UART OUT V Keymatrix Y3 Y2 Y4 Y1 74 AC 04 Figure 2-2 Improved Circuit to Suppress Water Films X2 X3 X4 X5 X6 X7 X8 YS1 YS2 YS3 YS4 CC 1 CC 2 CS AIN G GGG VV V Vcc Rst Rx Tx I1 I2 I3 I4 O1 O2 O3 O4 O5 O6 O7 O8 XT1 XT2 L1 L2 4 9 10 33 34 35 36 11 12 13 14 23 24 25 26 8 7 15 16 618 39 V 517 27 3 8 40 41 42 43 44 1 2 3 19 20 21 22 32 31 30 37 28 29 DS18 11 8M H z CAL L ED STAT LED C6 (Cz 1) 820pF C 7 (Cz 2) 820p F BSN 20 R 2R dac 100K R3 68 K R5 1 0K R 4 100 K R6 10 K C 5 (C s) 15nF Vcc TLC 2272 UAR T IN UART OU T V Keymatrix Y3 Y2 Y4 Y1 QS3125 I/O I/O I/O I/O I/O I/O I/O I/O E E E E 22V10 Rt Ct + _ + _ |
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Similar Description - QT60320 |
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