Low-Power, Compact 2.5Gbps or 2.7Gbps

Clock-Recovery and Data-Retiming IC

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7

Detailed Description

The MAX3873 consists of a fully integrated phase-

locked loop (PLL), input amplifier, and CML output

buffers (Figure 5). The PLL consists of a phase/fre-

quency detector, a loop filter, and a voltage-controlled

oscillator (VCO).

This device is designed to deliver the best combination

of jitter performance and power dissipation by using a

fully-differential signal architecture and low-noise

design techniques.

Input Amplifier

The input amplifier provides internal 50Ω line termina-

tions and can accept a differential input amplitude from

amplifier is shown in Figure 9.

Phase Detector

The phase detector incorporated in the MAX3873 pro-

duces a voltage proportional to the phase difference

between the incoming data and the internal clock.

Because of its feedback nature, the PLL drives the

error voltage to zero, aligning the recovered clock to

the center of the incoming data eye for retiming.

Frequency Detector

The digital frequency detector (FD) aids frequency

acquisition during startup conditions. The frequency

difference between the received data and the VCO

clock is derived by sampling the VCO outputs on each

edge of the data input signal. The FD drives the VCO

until the frequency difference is reduced to zero. Once

frequency acquisition is complete, the FD returns to a

neutral state.

Loop Filter and VCO

The phase detector and frequency detector outputs are

is required to set the PLL damping ratio. See the

Design Procedure section for guidelines on selecting

this capacitor.

PIN

NAME

FUNCTION

10

SCLKEN

Clock Output Enable, TTL Input. When SCLKEN = OPEN or SCLKEN = High, the clock outputs

11

SCLKO-

Negative Clock Output, CML. This output can be disabled by setting SCLKEN to Low.

12

SCLKO+

Positive Clock Output, CML. This output can be disabled by setting SCLKEN to Low.

13

VCC_BUF

3.3V CML Output Buffer Supply Voltage

14

SDO-

Negative Data Output, CML

15

SDO+

Positive Data Output, CML

16

LOL

Loss-of-Lock Output, TTL (Active-Low). The

LOL output indicates a PLL lock failure.

17, 20

GND

Supply Ground

18

FIL-

Negative PLL Loop Filter Connection. Connect a 0.01µF capacitor between FIL+ and FIL-.

19

FIL+

Positive PLL Loop Filter Connection. Connect a 0.01µF capacitor between FIL+ and FIL-.

EP

Exposed Pad

Ground. The exposed pad must be soldered to the circuit board ground for proper electrical and

thermal operation.

Pin Description (continued)

Figure 5. Functional Diagram

RATESET

FIL-

FIL+

GND

MAX3873

LOOP

FILTER

FASTRACK

SDO+

SDO-

SDI+

SDI-

SCLKO+

SCLKO-

SCLKEN

MODE

AMP

AMP

AMP

I

Q

PHASE AND

FREQUENCY

DETECTOR

LOL

VCO