Low-Power, Compact 2.5Gbps or 2.7Gbps

Clock-Recovery and Data-Retiming IC

4

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Figure 1. Definition of Input Voltage Swing

Figure 2. Definition of Clock-to-Q Delay

(a) AC-COUPLED SINGLE-ENDED INPUT (CML OR PECL)

(b) DC-COUPLED SINGLE-ENDED CML INPUT

25mV

25mV

800mV

800mV

SCLKO+

SDO

Figure 4. Definition of LOL Assert Time and Frequency Acquisition Time

INPUT DATA

FREQUENCY ACQUISITION TIME

LOL OUTPUT

LOL ASSERT TIME

Figure 3. Definition of Phase Acquisition Time

SERIAL DATA

1200 BITS OF 1–0 PATTERN

<2µs

FASTRACK

DATA

VCO CLOCK PHASE ALIGNED TO INPUT DATA