LTC3717 datasheet(6/20 Pages) LINER

Part #	LTC3717

Description	Wide Operating Range, No RSENSE Step-Down Controller for DDR/QDR Memory Termination

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Manufacturer	LINER [Linear Technology]

Direct Link	http://www.linear.com

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LTC3717

sn3717 3717fs

PI FU CTIO S

RUN/SS (Pin 1): Run Control and Soft-Start Input. A

capacitor to ground at this pin sets the ramp time to full

output current (approximately 3s/

µF) and the time delay

for overcurrent latchoff (see Applications Information).

Forcing this pin below 0.8V shuts down the device.

PGOOD (Pin 2): Power Good Output. Open drain logic

output that is pulled to ground when the output voltage is

not within

±10% of the regulation point.

VRNG (Pin 3): Sense Voltage Range Input. The voltage at

this pin is ten times the nominal sense voltage at maxi-

mum output current and can be set from 0.5V to 2V by a

resistive divider from INTVCC. The nominal sense voltage

defaults to 70mV when this pin is tied to ground, 140mV

when tied to INTVCC.

ITH (Pin 4): Current Control Threshold and Error Amplifier

Compensation Point. The current comparator threshold

increases with this control voltage. The voltage ranges

from 0V to 2.4V with 0.8V corresponding to zero sense

voltage (zero current).

SGND (Pin 5): Signal Ground. All small-signal compo-

nents and compensation components should connect to

this ground, which in turn connects to PGND at one point.

ION (Pin 6): On-Time Current Input. Tie a resistor from VIN

to this pin to set the one-shot timer current and thereby set

the switching frequency.

VFB (Pin 7): Error Amplifier Feedback Input. This pin

connects to VOUT and divides its voltage to 2/3 • VFB

through precision internal resistors before it is applied to

the input of the error amplifier. Do not apply more than

1.5V on VFB. For higher output voltages, attach an external

resistor R2 (1/2 • R1 at VREF) from VOUT to VFB.

VREF (Pin 8): Positive Input of Internal Error Amplifier.

This pin connects to an external reference and divides its

voltage to 1/3 VREF through precision internal resisters

before it is applied to the positive input of the error

amplifier. Reference voltage for output voltage, power

good threshold, and short-circuit shutdown threshold. Do

not apply more than 3V on VREF. If higher voltages are

used, connect an external resistor (R1

≥ 160k) from

voltage reference to VREF.

EXTVCC (Pin 9): External VCC Input. When EXTVCC ex-

ceeds 4.7V, an internal switch connects this pin to INTVCC

and shuts down the internal regulator so that controller

and gate drive power is drawn from EXTVCC. Do not exceed

7V at this pin and ensure that EXTVCC < VCC.

VCC (Pin 10): Bias Input Supply. 4V to 36V operating

range. Decouple this pin to PGND with an RC filter (1

Ω,

0.1

µF).

INTVCC (Pin 11): Internal 5V Regulator Output. The driver

and control circuits are powered from this voltage. De-

couple this pin to power ground with a minimum of 4.7

µF

low ESR tantalum or ceramic capacitor.

BG (Pin 12): Bottom Gate Drive. Drives the gate of the

bottom N-channel MOSFET between ground and INTVCC.

PGND (Pin 13): Power Ground. Connect this pin closely to

the source of the bottom N-channel MOSFET, the (–)

terminal of CVCC and the (–) terminal of CIN.

SW (Pin 14): Switch Node. The (–) terminal of the boot-

strap capacitor CB connects here. This pin swings from a

diode voltage drop below ground up to a diode voltage

drop above VIN.

TG (Pin 15): Top Gate Drive. Drives the top N-channel

MOSFET with a voltage swing equal to INTVCC superim-

posed on the switch node voltage SW.

BOOST (Pin 16): Boosted Floating Driver Supply. The (+)

terminal of the bootstrap capacitor CB connects here. This

pin swings from a diode voltage drop below INTVCC up to

VIN + INTVCC.

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