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AD9410 Datasheet(PDF) 11 Page - Analog Devices |
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AD9410 Datasheet(HTML) 11 Page - Analog Devices |
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11 / 21 page  AD9410 Rev. A | Page 10 of 20 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the clock command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180° and taking the peak measurement again. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) ENOB is calculated from the measured SINAD based on the equation 02 . 6 log 20 76 . 1 ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ + − = Amplitude Input Amplitude Scale Full dB SINAD ENOB MEASURED Clock Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in Logic 1 state to achieve rated performance; pulse width low is the minimum time the clock pulse should be left in low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Full-Scale Input Power Expressed in dBm. Computed using the equation ⎥ ⎥ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎢ ⎢ ⎣ ⎡ = 001 . 0 log 10 2 INPUT FULLSCALE FULLSCALE Z V POWER rms Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least-square curve fit. Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The clock rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of CLK+ and CLK− and the time when all output data bits are within valid logic levels. Out-of-Range Recovery Time Out-of-range recovery time is the time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Noise (For Any Range Within the ADC) ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ − × × = 10 10 001 . 0 | | dBFS dBm NOISE SIGNAL FS Z V where: Z is the input impedance. FS is the full scale of the device for the frequency in question. SIGNAL is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise. Power Supply Rejection Ratio (PSRR) The ratio of a change in input offset voltage to a change in power supply voltage. |
Similar Part No. - AD9410_17 |
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Similar Description - AD9410_17 |
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